SBOSAA7 September   2025 OPA598

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Current Limit
      2. 6.3.2 Overcurrent Flag
      3. 6.3.3 Overtemperature Flag
      4. 6.3.4 Enable and Disable
      5. 6.3.5 Mux-Friendly Inputs
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 High Voltage 2:1 Multiplexer With Unity Gain
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Output Driver
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curve
      3. 7.2.3 Parallel Op Amps
      4. 7.2.4 Composite Amplifier
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 TI Precision Designs
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

at VS = 85V, TA = 25°C, RL = 10kΩ to mid-supply, IOUT limit set to 100mA, and VCM = VOUT = mid-supply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±50 ±1 mV
dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±1 ±5 µV/°C
PSRR Power supply rejection ratio VS = ±4V to ±42.5V 0.1 1.5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±1 ±10 pA
TA = –40°C to +85°C ±350
TA = –40°C to +125°C ±5 nA
IOS Input offset current ±1 ±5 pA
TA = –40°C to +85°C ±250
TA = –40°C to +125°C ±1 nA
NOISE
Input voltage noise f = 0.1Hz to 10Hz 2.9 µVPP
en Input voltage noise density f = 10Hz 75 nV/√Hz
f = 1kHz 10
f = 10kHz 7
in Current noise density f = 1kHz 12 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage Linear operation (V–) – 0.1 (V+) – 3.5 V
CMRR Common-mode rejection (V–) ≤ VCM ≤ (V+) – 3.5V 120 140 dB
TA = –40°C to +125°C 106 124
INPUT IMPEDANCE
Differential 1013 || 0.3 Ω || pF
Common-mode 1013 || 9.4 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.3V < VO < (V+) – 0.3V,
RL = 10kΩ		 130 140 dB
TA = –40°C to +125°C 130 140
(V–) + 1V < VO < (V+) – 1V,
RL = 2kΩ		 120 130
TA = –40°C to +125°C 120 130
(V–) + 2.5V < VO < (V+) – 2.5V,
RL = 600Ω		 130 135
TA = –40°C to +125°C 125 130
FREQUENCY RESPONSE
GBW Gain-bandwidth product 10 MHz
SR Slew rate Gain = ±1, VOUT = 70V step Rising 45 V/µs
Falling 35
tS Settling time To ±0.01%, gain = –1, VOUT = 70V step, CL = 100pF 2.9 µs
THD+N Total harmonic distortion + noise Gain = +1, VOUT = 70VPP,
f = 1kHz		 RL = 600Ω –105 dB
RL = 2kΩ –110
OUTPUT
VO Voltage output swing from rail Sourcing,
RCL = 0Ω connected to V–		 No load 40 50 mV
IOUT = 50mA 450 600
IOUT = 100mA 0.75 1.1 V
IOUT = 250mA 2.5 3
RL = 2kΩ 125 mV
RL = 10kΩ 750
Sinking,
RCL = 0Ω connected to V–		 No load 10 25 mV
IOUT = 50mA 450 600
IOUT = 100mA 0.75 1.1 V
IOUT = 250mA 2.5 3
RL = 2kΩ 125 mV
RL = 10kΩ 750
Continuous output current, dc VS = 85V, RCL = 0Ω, ILIMIT = 250mA ±300 mA
CLOAD Capacitive load drive See typical curves pF
ZO Open-loop output impedance See typical curves Ω
Output impedance Output disabled, V– < VOUT < V+ 100 MΩ
Output capacitance Output disabled 56 pF
CURRENT LIMIT
Current limit accuracy(2)(3) Sourcing,
RL = 10Ω to mid-supply		 ILIMIT = 50mA,
VLIMIT =  3.137V		 46 mA
ILIMIT = 100mA,
VLIMIT =  2.587V		 100
ILIMIT = 250mA,
VLIMIT =  0.937V		 250
Sinking,
RL = 10Ω to mid-supply		 ILIMIT = 50mA,
VLIMIT =  3.137V		 56
ILIMIT = 100mA,
VLIMIT =  2.587V		 108
ILIMIT = 250mA,
VLIMIT =  0.937V		 265
Current limit equation Resistor set, RCL connected between ILIMIT pin and V– (3.687V × 4000) / (44kΩ + RCL) mA
Voltage set, VLIMIT connected to ILIMIT pin and referenced to V– 4000 × (3.687V – VLIMIT) / 44kΩ
STATUS FLAG PIN (Referenced to E/D Com)
Status flag delay Overcurrent delay 10 µs
Overcurrent recovery delay 10
Thermal shutdown Alarm (status flag high) 170 °C
Return to normal operation (status flag low) 150
Status flag output voltage Normal operation See typical curves
E/D PIN
VE/D E/D voltage(1) Enable, pin open or forced high E/D Com + 1.5 E/D Com + 5.5 V
Disable, pin forced low E/D Com E/D Com + 0.5
IE/D E/D input current 50 µA
Output disable time 12 µs
Output enable time 18 µs
E/D COM PIN
E/D Com voltage (V–) (V+) – 6 V
POWER SUPPLY
IQ Quiescent current 3.25 3.75 mA
TA = –40°C to +125°C 4
Output disabled 0.25
(1) For information on the output enable and disable feature see Section 7.3.4.
(2) Proper output swing headroom is necessary to maintain current limit accuracy.
(3) A current source forces a current equal to ILIMIT / 4000 into the ILIMIT pin.