SBOSAG3A March   2024  – December 2024 PGA849

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Control
      2. 7.3.2 Input Protection
      3. 7.3.3 Using the Output Difference Amplifier to Shape Noise
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Linear Operating Input Range
      2. 8.1.2 Current Consumption with Differential Inputs
    2. 8.2 Typical Applications
      1. 8.2.1 Driving a Single-Ended Input SAR ADC
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RGT Package, 16-Pin VQFN (Top View)
Table 5-1 Pin Functions
PINTYPEDESCRIPTION
NAMENO.
A04InputGain option pin 0
A15InputGain option pin 1
A21InputGain option pin 2
DA_IN+9InputConnection to output difference amplifier summing node
DA_IN–12InputConnection to output difference amplifier summing node
DGND 16 Power Ground reference for digital-logic and gain-setting pins
IN–3InputNegative (inverting) input
IN+2InputPositive (noninverting) input
LVDD7PowerOutput-driver positive supply
LVSS14PowerOutput-driver negative supply
NC8—Do not connect
NC 13 — Do not connect
OUT11OutputOutput
REF10InputReference input. This pin must be driven by a low-impedance source
VS+6PowerInput-stage positive supply
VS–15PowerInput-stage negative supply
Thermal PadThermal pad—The thermal pad must be soldered to the printed-circuit board (PCB). Connect thermal pad to a plane or large copper pour that is either floating or electrically connected to VS–, even for applications that have low power dissipation.