SBOU162A March   2017  – May 2017

 

  1.   DIYAMP-SOIC-EVM
    1.     Trademarks
    2. 1 Introduction
      1. 1.1 DIYAMP-SOIC-EVM Kit Contents
      2. 1.2 EVM Features
      3. 1.3 List of Circuits on the EVM
    3. 2 Hardware Setup
      1. 2.1 EVM Circuit Locations
      2. 2.2 EVM Assembly Instructions
    4. 3 Schematic and PCB Layout
      1. 3.1  Schematic PCB Drawing
      2. 3.2  Single-Supply, Multiple Feedback Filter
      3. 3.3  Single-Supply, Sallen-Key Filter
      4. 3.4  Single-Supply, Non-Inverting Amplifier
      5. 3.5  Single-Supply, Inverting Amplifier
      6. 3.6  Difference Amplifier
      7. 3.7  Dual-Supply, Multiple Feedback Filter
      8. 3.8  Dual-Supply, Sallen-Key Filter
      9. 3.9  Inverting Comparator
      10. 3.10 Non-Inverting Comparator
      11. 3.11 Riso With Dual Feedback
      12. 3.12 Dual-Supply, Non-Inverting Amplifier
      13. 3.13 Dual-Supply, Inverting Amplifier
    5. 4 Connections
      1. 4.1 Inputs and Outputs
      2. 4.2 Power
      3. 4.3 Enable and Disable Feature
    6. 5 Bill of Materials and Reference
      1. 5.1 Bill of Materials
      2. 5.2 Reference
  2.   Revision History

Inverting Comparator

Figure 30 shows the schematic for the inverting comparator circuit configuration.

diyamp_nfig30_inverting_comp_sch.pngFigure 30. Inverting Comparator Schematic

It is important to note that this circuit layout is meant for SOIC package op amps or push-pull output type comparators. This configuration uses a voltage divider R1 and R2 to set up the threshold voltage when no hysteresis is added. The comparator will compare the input signal (Vin) to the threshold voltage (Vth).

Equation 18. nneq18_sbou162.gif

    where

  • R3 is unpopulated

The comparator input signal is applied to the inverting input, so the output will have an inverted polarity. When Vin > Vth, the output will drive to the negative supply (GND or logic low). When Vin < Vth, the output will drive to the positive supply (V+ or logic high).

R3 can be populated to implement hysteresis which uses two different threshold voltages to avoid the multiple transitions. The input signal must exceed the upper threshold (VH) to transition low or below the lower threshold (VL) to transition high. Equation 19 and Equation 20 will calculate the value of R2 and R3 for the two desired thresholds.

Equation 19. nneq19_sbou162.gif
Equation 20. nneq20_sbou162.gif

The PCB layout of the top layer of the inverting comparator circuit configuration is displayed in Figure 31.

diyamp_nfig31_invert_comp_toplayer.pngFigure 31. Inverting Comparator Top Layer

The PCB layout of the bottom layer of the inverting comparator circuit configuration is displayed in Figure 32.

diyamp_nfig32_invert_comp_botlayer.pngFigure 32. Inverting Comparator Bottom Layer