SBOU162A March   2017  – May 2017

 

  1.   DIYAMP-SOIC-EVM
    1.     Trademarks
    2. 1 Introduction
      1. 1.1 DIYAMP-SOIC-EVM Kit Contents
      2. 1.2 EVM Features
      3. 1.3 List of Circuits on the EVM
    3. 2 Hardware Setup
      1. 2.1 EVM Circuit Locations
      2. 2.2 EVM Assembly Instructions
    4. 3 Schematic and PCB Layout
      1. 3.1  Schematic PCB Drawing
      2. 3.2  Single-Supply, Multiple Feedback Filter
      3. 3.3  Single-Supply, Sallen-Key Filter
      4. 3.4  Single-Supply, Non-Inverting Amplifier
      5. 3.5  Single-Supply, Inverting Amplifier
      6. 3.6  Difference Amplifier
      7. 3.7  Dual-Supply, Multiple Feedback Filter
      8. 3.8  Dual-Supply, Sallen-Key Filter
      9. 3.9  Inverting Comparator
      10. 3.10 Non-Inverting Comparator
      11. 3.11 Riso With Dual Feedback
      12. 3.12 Dual-Supply, Non-Inverting Amplifier
      13. 3.13 Dual-Supply, Inverting Amplifier
    5. 4 Connections
      1. 4.1 Inputs and Outputs
      2. 4.2 Power
      3. 4.3 Enable and Disable Feature
    6. 5 Bill of Materials and Reference
      1. 5.1 Bill of Materials
      2. 5.2 Reference
  2.   Revision History

Riso With Dual Feedback

Figure 36 shows the schematic for the Riso with dual-feedback circuit configuration.

fig23_sbou162.pngFigure 36. Riso with Dual-Feedback Schematic

The dc gain of the Riso with dual-feedback circuit configuration can be calculated using Equation 24.

Equation 24. nneq24_sbou162.gif

In situations where stability is affected by capacitive loads, the Riso dual-feedback configuration has the ability to stabilize the circuit by compensating the contribution of the capacitive load to circuit instability. This capacitive load compensation technique uses an isolation resistor that compensates the circuit by adding a zero to cancel the pole from the output impedance and capacitive load. Refer to the TI Precision Labs - Op Amps: Stability 5 video for detailed information on this technique.

The design steps for the Riso method follow:

  1. Use TINA-TI™ to find the zero frequency, fZERO, where AOL_Loaded = 20 dB (example shown in Figure 37).
  2. diyamp_nfig37_example_fzero_aol_loaded.pngFigure 37. Example of fZERO, Where AOL_Loaded = 20 dB
  3. Calculate Riso to set the zero at fZERO – this will yield between 60° and 90° of phase margin
  4. Equation 25. nneq25_sbou162.gif

      where

    • Riso = R3
    • CLoad = C4

While the Riso circuit is both simple to implement and design, it has a big disadvantage in precision circuits. The voltage drop from Riso is dependent on the output current or output load, and may be significant compared to the desired signal.

The second capacitive load compensation technique uses the Riso with dual-feedback stability compensation method. The Riso dual-feedback circuit solves the voltage drop disadvantage of the previously stated Riso. Refer to the TI Precision Labs - Op Amps: Stability 6 video for detailed information on this technique.

Design steps for the Riso method follow:

  1. Riso using Method 1: Riso techniques
  2. Set R1: R1 ≥ (Riso × 100)
  3. Set C1: nnInline_Eq01_sbou162.gif

Using this range ensures that the two feedback paths, R2 and C3, will never create a resonance that would cause instability. Smaller values of C3 will result in faster settling time at the expense of overshoot for certain load ranges. While the Riso dual-feedback circuit solves the dc accuracy issue with the Riso circuit, it has some disadvantages as well. The disadvantage of this method is that the circuit is not as tolerant to changes in the output capacitance and can quickly become unstable. Therefore, the Riso dual-feedback circuit is best for situations where the output capacitance is known and will not vary significantly. This method generally results in a slower settling time than the Riso circuit as well.

The PCB layout of the top layer of the Riso dual-feedback amplifier circuit configuration is displayed in Figure 38

diyamp_nfig38_DS_noninvert_amp_toplayer.pngFigure 38. Riso Dual-Feedback Top Layer

The PCB layout of the bottom layer of the Riso dual-feedback amplifier circuit configuration is displayed in Figure 39.

diyamp_nfig39_DS_noninvert_amp_bottomlayer.pngFigure 39. Riso Dual-Feedback Bottom Layer