SBOU162A March   2017  – May 2017

 

  1.   DIYAMP-SOIC-EVM
    1.     Trademarks
    2. 1 Introduction
      1. 1.1 DIYAMP-SOIC-EVM Kit Contents
      2. 1.2 EVM Features
      3. 1.3 List of Circuits on the EVM
    3. 2 Hardware Setup
      1. 2.1 EVM Circuit Locations
      2. 2.2 EVM Assembly Instructions
    4. 3 Schematic and PCB Layout
      1. 3.1  Schematic PCB Drawing
      2. 3.2  Single-Supply, Multiple Feedback Filter
      3. 3.3  Single-Supply, Sallen-Key Filter
      4. 3.4  Single-Supply, Non-Inverting Amplifier
      5. 3.5  Single-Supply, Inverting Amplifier
      6. 3.6  Difference Amplifier
      7. 3.7  Dual-Supply, Multiple Feedback Filter
      8. 3.8  Dual-Supply, Sallen-Key Filter
      9. 3.9  Inverting Comparator
      10. 3.10 Non-Inverting Comparator
      11. 3.11 Riso With Dual Feedback
      12. 3.12 Dual-Supply, Non-Inverting Amplifier
      13. 3.13 Dual-Supply, Inverting Amplifier
    5. 4 Connections
      1. 4.1 Inputs and Outputs
      2. 4.2 Power
      3. 4.3 Enable and Disable Feature
    6. 5 Bill of Materials and Reference
      1. 5.1 Bill of Materials
      2. 5.2 Reference
  2.   Revision History

Non-Inverting Comparator

Figure 33 shows the schematic for the non-inverting comparator circuit configuration.

diyamp_nfig33_noninv_comp_sch.gifFigure 33. Non-Inverting Comparator Schematic

It is important to note that this circuit layout is meant for SOIC package op amp or push-pull output type comparators. This configuration uses a voltage divider R3 and R4 to set up the threshold voltage. The comparator will compare the input signal (Vin) to the threshold voltage (Vth).

Equation 21. nneq21_sbou162.gif

The comparator input signal is applied to the non-inverting input, so the output will have a non-inverted polarity. When Vin > Vth, the output will drive to the positive supply (V+ or logic high). When Vin < Vth, the output will drive to the negative supply (GND or logic low).

R2 can be populated to implement hysteresis which uses two different threshold voltages to avoid the multiple transitions. The input signal must exceed the upper threshold (VH) to transition high or below the lower threshold (VL) to transition low. Equation 22 and Equation 23 will calculate the value of R1 and R2 for the two desired thresholds.

Equation 22. nneq22_sbou162.gif
Equation 23. nneq23_sbou162.gif

The PCB layout of the top layer of the non-inverting comparator circuit configuration is displayed in Figure 34.

diyamp_nfig34_noninvert_comp_toplayer.pngFigure 34. Non-inverting Comparator Top Layer

The PCB layout of the top layer of the non-inverting comparator circuit configuration is displayed in Figure 35.

diyamp_nfig35_noninvert_comp_bottomlayer.pngFigure 35. Non-Inverting Comparator Bottom Layer