SBVS324B June   2017  – September 2026 TPS7A90

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage (VDO)
      3. 6.3.3 Output Voltage Accuracy
      4. 6.3.4 High Power-Supply Rejection Ratio (PSRR)
      5. 6.3.5 Low Output Noise
      6. 6.3.6 Output Soft-Start Control
      7. 6.3.7 Power-Good Function
      8. 6.3.8 Internal Protection Circuitry
        1. 6.3.8.1 Undervoltage Lockout (UVLO)
        2. 6.3.8.2 Internal Current Limit (ICL)
        3. 6.3.8.3 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Output
      2. 7.1.2 Start-Up
        1. 7.1.2.1 Enable (EN) and Undervoltage Lockout (UVLO)
        2. 7.1.2.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
          1. 7.1.2.2.1 Noise Reduction
          2. 7.1.2.2.2 Soft-Start and In-Rush Current
      3. 7.1.3 Capacitor Recommendation
        1. 7.1.3.1 Input and Output Capacitor Requirements (CIN and COUT)
          1. 7.1.3.1.1 Load-Step Transient Response
        2. 7.1.3.2 Feed-Forward Capacitor (CFF)
      4. 7.1.4 Power Dissipation (PD)
      5. 7.1.5 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 SPICE Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

over operating temperature range (TJ = –40°C to +125°C), 1.4V ≤ VIN ≤ 6.5V, VOUT(NOM) = 0.8V, IOUT = 5mA, VEN = 1.4V, CIN = COUT = 10μF, CNR/SS = CFF = 0nF, SS_CTRL = GND, and PG pin pulled up to VIN with 100kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input supply voltage range 1.4 6.5 V
VREF Reference voltage 0.8 V
VUVLO Input supply UVLO VIN rising 1.31 1.39 V
VHYS(UVLO) Input supply UVLO hysteresis 290 mV
VOUT Output voltage range 0.8 5.7 V
Output voltage accuracy(1) 1.4V ≤ VIN ≤ 6.5V, 5mA ≤ IOUT ≤ 0.5A –1.0% 1.0%
ΔVOUT(ΔVIN) Line regulation 0.005 %/V
ΔVOUT(ΔIOUT) Load regulation(2) 5mA ≤ IOUT ≤ 0.5A 0.02 %/A
VDO Dropout voltage 1.4V ≤ VIN ≤ 5.0V, IOUT = 0.5A, VFB = 0.8V – 3% 100 mV
5.0V < VIN ≤ 5.7V, IOUT = 0.5A, VFB = 0.8V – 3% 200
ILIM Output current limit VOUT forced at 0.9 × VOUT(NOM),
VIN = VOUT(NOM) + 300mV		 0.8 1.1 1.5 A
IGND GND pin current VIN = 6.5V, IOUT = 5mA 2.1 3.5 mA
VIN = 1.4V, IOUT = 0.5A 4
ISDN Shutdown GND pin current PG = (open), VIN = 6.5V, VEN = 0.4V 0.1 15 µA
IEN EN pin current VIN = 6.5V, 0V ≤ VEN ≤ 6.5V –0.2 0.2 µA
VIL(EN) EN pin low-level input voltage (device disabled) 0 0.4 V
VIH(EN) EN pin high-level input voltage (device enabled) 1.1 6.5 V
ISS_CTRL SS_CTRL pin current VIN = 6.5V, 0V ≤ VSS_CTRL ≤ 6.5V –0.2 0.2 µA
VIT(PG+) PG pin threshold rising For PG transitioning low with rising VOUT, expressed as a percentage of VOUT(NOM) 84% 90.9% 95%
VIT(PG–) PG pin threshold falling For PG transitioning low with falling VOUT, expressed as a percentage of VOUT(NOM) 82% 88.9% 93%
VHYS(PG) PG pin hysteresis For PG transitioning high with rising VOUT, expressed as a percentage of VOUT(NOM) 1%
VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = –1mA (current into device) 0.4 V
ILKG(PG) PG pin leakage current VOUT > VIT(PG), VPG = 6.5V 1 µA
INR/SS NR/SS pin charging current VNR/SS = GND, VSS_CTRL = GND 4.0 6.2 9.0 µA
VNR/SS = GND, VSS_CTRL = VIN 65 100 150
IFB FB pin leakage current VIN = 6.5V, VFB = 0.8V –100 100 nA
PSRR Power-supply ripple rejection f = 500kHz, VIN = 3.8V, VOUT(NOM) = 3.3V,
IOUT = 250mA, CNR/SS = 10nF, CFF = 10nF		 39 dB
Vn Output noise voltage BW = 10Hz to 100kHz, VIN = 1.8V, VOUT(NOM) = 0.8V,
IOUT = 0.5A, CNR/SS = 10nF, CFF = 10nF		 4.7 µVRMS
Noise spectral density f = 10kHz, VIN = 1.8V, VOUT(NOM) = 0.8V,
IOUT = 0.5A, CNR/SS = 10nF, CFF = 10nF		 13 nV/√ Hz
Rdiss Output active discharge resistance VEN = GND 250 Ω
Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140
(1) When the device connects to external feedback resistors at the FB pin, external resistor tolerances are not included.
(2) The device is not tested under conditions where VIN > VOUT + 2.5V and IOUT = 0.5A because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.