SBVS324B June   2017  – September 2026 TPS7A90

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage (VDO)
      3. 6.3.3 Output Voltage Accuracy
      4. 6.3.4 High Power-Supply Rejection Ratio (PSRR)
      5. 6.3.5 Low Output Noise
      6. 6.3.6 Output Soft-Start Control
      7. 6.3.7 Power-Good Function
      8. 6.3.8 Internal Protection Circuitry
        1. 6.3.8.1 Undervoltage Lockout (UVLO)
        2. 6.3.8.2 Internal Current Limit (ICL)
        3. 6.3.8.3 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Output
      2. 7.1.2 Start-Up
        1. 7.1.2.1 Enable (EN) and Undervoltage Lockout (UVLO)
        2. 7.1.2.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
          1. 7.1.2.2.1 Noise Reduction
          2. 7.1.2.2.2 Soft-Start and In-Rush Current
      3. 7.1.3 Capacitor Recommendation
        1. 7.1.3.1 Input and Output Capacitor Requirements (CIN and COUT)
          1. 7.1.3.1.1 Load-Step Transient Response
        2. 7.1.3.2 Feed-Forward Capacitor (CFF)
      4. 7.1.4 Power Dissipation (PD)
      5. 7.1.5 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 SPICE Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.7 Power-Good Function

The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. When the feedback pin voltage falls below the PG threshold voltage (VIT(PG)), the PG pin open-drain output engages and pulls the PG pin close to GND. When the feedback voltage exceeds the VIT(PG) threshold by an amount greater than VHYS(PG), the PG pin becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices. TI recommends using a pullup resistor from 10kΩ to 100kΩ. TI also recommends using an external reset device such as the TPS3890 in applications where high accuracy is needed or in applications where microprocessor induced resets are needed.

When using a feed-forward capacitor (CFF), the time constant for the LDO startup is increased whereas the power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output. To avoid this issue and to receive a valid PG output, make sure that the time constant of both the LDO startup and the power-good output are matching, which can be done by adding a capacitor in parallel with the power-good pullup resistor. See also the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note .

The state of PG is only valid when the device is operating above the minimum input voltage of the device and power-good is asserted regardless of the output voltage state when the input voltage falls below the UVLO threshold minus the UVLO hysteresis. Figure 6-2 shows a simplified block diagram of the power-good circuit. When the input voltage falls below approximately 0.8V, there is not enough gate drive voltage to keep the open-drain, power-good device turned on and the power-good output is pulled high. Connecting the power-good pullup resistor to the output voltage can help minimize this effect.

TPS7A90 Simplified PG CircuitFigure 6-2 Simplified PG Circuit