SBVS419B March   2022  – March 2026 TPS3760-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 SENSE Hysteresis
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Push-Pull
        3. 7.3.3.3 Active-High (RESET)
        4. 7.3.3.4 Active-Low (RESET)
      4. 7.3.4 User-Programmable Reset Time Delay
        1. 7.3.4.1 Reset Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Manual RESET (CTR / MR) Input
      7. 7.3.7 RESET Latch Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Adjustable Voltage Thresholds
    3. 8.3 Typical Application
      1. 8.3.1 Design 1: Off-Battery Monitoring
        1. 8.3.1.1 Design Requirements
        2. 8.3.1.2 Detailed Design Procedure
        3. 8.3.1.3 Application Curves
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Dissipation and Device Operation
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
      3. 8.5.3 Creepage Distance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.7 Timing Diagrams

TPS3760-Q1 Voltage Threshold and Hysteresis AccuracyFigure 6-1 Voltage Threshold and Hysteresis Accuracy
TPS3760-Q1 SENSE Undervoltage (UV) Timing Diagram
A. For open-drain output option, the timing diagram assumes the RESET_UVOD / RESET_UVOD pin is connected via an external pull-up resistor to VDD.
B. Be advised that Figure 6-2 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTR) time.
C. RESET_UVxx / RESET_UVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTR, is reached.
Figure 6-2 SENSE Undervoltage (UV) Timing Diagram
TPS3760-Q1 SENSE Overvoltage (OV) Timing Diagram
A. For open-drain output option, the timing diagram assumes the RESET_OVOD / RESET_OVOD pin is connected via an external pull-up resistor to VDD.
B. Be advised that Figure 6-3 shows the VDD falling slew rate is slow or the VDD decay time is much larger than the propagation detect delay (tCTR) time.
C. RESET_OVxx / RESET_OVxx is asserted when VDD goes below the UVLO(MIN) threshold after the time delay, tCTR, is reached.
Figure 6-3 SENSE Overvoltage (OV) Timing Diagram