SBVS425B December   2022  – June 2025 TPS748A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics: IOUT = 50mA
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable and Shutdown
      2. 6.3.2 Active Discharge
      3. 6.3.3 Power-Good Output (PG)
      4. 6.3.4 Internal Current Limit
      5. 6.3.5 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input, Output, and Bias Capacitor Requirements
      2. 7.1.2 Dropout Voltage
      3. 7.1.3 Output Noise
      4. 7.1.4 Estimating Junction Temperature
      5. 7.1.5 Soft Start, Sequencing, and Inrush Current
      6. 7.1.6 Power-Good Operation
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TPS748A-Q1 DRC Package,10-Pin VSON With Thermal Pad(Top View) Figure 4-1 DRC Package,10-Pin VSON With Thermal Pad(Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME VSON
BIAS 4 I Bias input voltage for the error amplifier, reference, and internal control circuits. Use a 1µF or larger input capacitor for optimal performance. If IN is connected to BIAS, use a 4.7µF or larger capacitor.
EN 5 I Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. Do not leave this pin unconnected.
FB 8 I Feedback pin. This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. Do not leave this pin floating.
GND 6 — Ground
IN 1, 2 I Input to the device. Use a 1µF or larger input capacitor for optimal performance.
NC N/A — No connection. Leave this pin floating or connected to GND to allow better thermal contact to the top-side plane.
OUT 9, 10 O Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2μF, ceramic) is needed from this pin to ground to provide stability.
PG 3 O Power-good pin. This pin is an open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. Connect a pullup resistor (10kΩ to 1MΩ) from this pin to a supply of up to 6.0V. A supply higher than the input voltage is permissible. Alternatively, leave the PG pin unconnected if output monitoring is not necessary.
SS 7 — Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left unconnected, the regulator output soft-start ramp time is typically 200μs.
Thermal pad — Solder this pad to the ground plane for increased thermal performance. This pad is internally connected to ground.