SCAS293M January   1993  – June 2026 SN74LVC240A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   5
  6.   6
  7. 4 Pin Configuration and Functions
  8. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics, –40°C to 85°C
    7. 5.7 Switching Characteristics, –40°C to 125°C
    8. 5.8 Operating Characteristics
    9. 5.9 Typical Characteristics
  9. 6 Parameter Measurement Information
  10. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Partial Power Down (Ioff)
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  11. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  12. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  13.   49
  14. 10Revision History
  15. 11Mechanical, Packaging, and Orderable Information

7.1 Overview

The SN74LVC240A contains 8 individual high speed CMOS inverters with Schmitt-trigger inputs and 3-state outputs.

Each inverter performs the Boolean logic function xYn = xAn, with x being the bank number and n being the channel number.

Each output enable (xOE) controls four inverters. When the xOE pin is in the low state, the outputs of all inverters in the bank x are enabled. When the xOE pin is in the high state, the outputs of all inverters in the bank x are disabled. All disabled output are placed into the high-impedance state.

To confirm the high-impedance state during power up or power down, both OE pins must be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver and the leakage of the pin as defined in the Electrical Characteristics table.