SCASE56 January   2025 SN74LV8T139-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Block Diagram
    4. 7.4 Feature Description
      1. 7.4.1 Balanced CMOS Push-Pull Outputs
      2. 7.4.2 LVxT Enhanced Input Voltage
        1. 7.4.2.1 Up Translation
        2. 7.4.2.2 Down Translation
      3. 7.4.3 Clamp Diode Structure
    5. 7.5 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

3 Description

The SN74LV8T139-EP contains two two-to-four decoders with one active low output strobe G. When the outputs of one channel are gated by the strobe input, they are all forced into the high state. When the outputs are not disabled by the strobe input, only the selected output is low while all others are high.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN74LV8T139-EP PW (TSSOP, 16) 5mm × 6.4mm 5mm × 4.4mm
(1) For more information, see Mechanical Packaging and Orderable Information Section.
(2) The package size (length × width) is a nominal value and includes pins, where applicable
(3) The body size (length × width) is a nominal value and does not include pins.
SN74LV8T139-EP Logic Diagram (Positive Logic) Logic Diagram (Positive Logic)