SCASE72 January   2025 SN54SC8T164-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Balanced CMOS Push-Pull Outputs
      2. 6.3.2 SCxT Enhanced Input Voltage
        1. 6.3.2.1 Up Translation
        2. 6.3.2.2 Down Translation
      3. 6.3.3 Clamp Diode Structure
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Typical Application
      1. 7.1.1 Application Information
      2. 7.1.2 Design Requirements
        1. 7.1.2.1 Power Considerations
        2. 7.1.2.2 Input Considerations
        3. 7.1.2.3 Output Considerations
      3. 7.1.3 Detailed Design Procedure
      4. 7.1.4 Application Curves
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

3 Description

The SN54SC8T164-SEP device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN54SC8T164-SEP PW (TSSOP, 14) 5.0mm × 6.4mm 5.0mm × 4.4mm
(1) For more information, see .
(2) The package size (length × width) is a nominal value and includes pins, where applicable
(3) The body size (length × width) is a nominal value and does not include pins.
SN54SC8T164-SEP Logic Diagram (Positive Logic) Logic Diagram (Positive Logic)