SCASE82 January   2026 TPUL2T122-Q1 , TPUL2T122A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Recommended Operating Conditions
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 State Machine Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Naming Convention
      2. 7.3.2 Retriggerable One-Shot
      3. 7.3.3 Timing Mechanism and Accuracy
      4. 7.3.4 Balanced CMOS Push-Pull Outputs
      5. 7.3.5 CMOS Schmitt-Trigger Inputs
      6. 7.3.6 Latching Logic with Known Power-Up State
      7. 7.3.7 Reduced Input Threshold Voltages
      8. 7.3.8 Wettable Flanks
      9. 7.3.9 Clamp Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off-State Operation
      2. 7.4.2 Startup Operation
      3. 7.4.3 On-State Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application - Edge Detector
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Timing Components
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
        4. 8.2.1.4 Power Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application - Delayed Pulse Generator
      1. 8.3.1 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TPUL2T122-Q1 TPUL2T122A-Q1 TPUL2T122-Q1D and PW Package16-Pin SOIC and TSSOPTop View
See mechanical drawings for dimensions.
Figure 4-1 TPUL2T122-Q1D and PW Package16-Pin SOIC and TSSOPTop View
TPUL2T122-Q1 TPUL2T122A-Q1 TPUL2T122-Q1BQB Package16-Pin WQFNTransparent Top View
See mechanical drawings for dimensions.
Figure 4-3 TPUL2T122-Q1BQB Package16-Pin WQFNTransparent Top View
TPUL2T122-Q1 TPUL2T122A-Q1 TPUL2T122A-Q1D and PW Package16-Pin SOIC and TSSOPTop View
See mechanical drawings for dimensions.
Figure 4-2 TPUL2T122A-Q1D and PW Package16-Pin SOIC and TSSOPTop View
TPUL2T122-Q1 TPUL2T122A-Q1 TPUL2T122A-Q1BQB Package16-Pin WQFNTransparent Top View
See mechanical drawings for dimensions.
Figure 4-4 TPUL2T122A-Q1BQB Package16-Pin WQFNTransparent Top View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME TPUL2T122-Q1 NO. TPUL2T122A-Q1 NO.
1C 14 1 G Channel 1 external timing capacitor negative connection; provides a return path for discharge current of the external timing capacitor; internally connected to ground
1CLR 3 3 I Channel 1 asynchronous clear input, active low
1Q 4 7 O Channel 1 inverted output
1Q 13 6 O Channel 1 output
1RC 15 2 I/O Channel 1 external timing node connection; see Application Information section for detailed operation instructions
1T 1 5 I

Channel 1 falling edge trigger input

TPUL2T122-Q1: Requires 1T and 1CLR to be held high

TPUL2T122A-Q1: Requires 1T to be held low and 1CLR to be held high
1T 2 4 I

Channel 1 rising edge trigger input

TPUL2T122-Q1: Requires 1T to be held low and 1CLR to be held high

TPUL2T122A-Q1: Requires 1T and 1CLR to be held high
2C 6 15 G Channel 2 external timing capacitor negative connection; provides a return path for discharge current of the external timing capacitor; internally connected to ground
2CLR 11 13 I Channel 2 asynchronous clear input, active low
2Q 5 10 O Channel 2 output
2Q 12 9 O Channel 2 inverted output
2RC 7 14 I/O Channel 2 external timing node connection; see Application Information section for detailed operation instructions
2T 9 11 I

Channel 2 falling edge trigger input

TPUL2T122-Q1: Requires 2T and 2CLR to be held high

TPUL2T122A-Q1: Requires 2T to be held low and 2CLR to be held high
2T 10 12 I

Channel 2 rising edge trigger input

TPUL2T122-Q1: Requires 2T to be held low and 2CLR to be held high

TPUL2T122A-Q1: Requires 2T and 2CLR to be held high
GND 8 8 G Ground
Thermal pad — The thermal pad can be connect to GND or left floating. Do not connect to any other signal or supply.
VCC 16 16 P Positive voltage supply
(1) I = Input, O = Output, I/O = Input and output, G = Ground, P = Power