SCDS034N July   1997  – June 2026 SN74CBTLV3245A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3.   Applications
  4. 2 Description
  5. 3 Pin Configuration and Functions
  6. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Thermal Information
    4. 4.4 Recommended Operating Conditions
    5. 4.5 Electrical Characteristics - DBQ, DGV, DW, PW and RGY only
    6. 4.6 Electrical Characteristics - RKS and DGS Package only
    7. 4.7 Switching Characteristics - DBQ, DGV, DW, PW and RGY only
    8. 4.8 Switching Characteristics - RKS and DGS Package only
    9. 4.9 Typical Characteristics
  7. 5 Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

2 Description

The SN74CBTLV3245A device provides 8 bits of high-speed bus switching in a standard '245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature maintains that damaging current does not backflow through the device when the device is powered down. The device has isolation during power off.

To maintain the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Package Information(1)
PART NUMBERPACKAGEPACKAGE SIZE(2)
SN74CBTLV3245ADBQ (SSOP, 20)8.65mm × 3.90mm
PW (TSSOP, 20)6.50mm × 4.40mm
RGY (VQFN, 20)4.50mm × 3.50mm
DW(SOIC, 20)12.80mm × 7.50mm
DGV(TVSOP, 20)5.00mm × 4.40mm
DGS(VSSOP, 20)5.10mm × 3.00mm
RKS(VQFN, 20)4.50mm × 2.50mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
SN74CBTLV3245A Logic Diagram (Positive Logic)Logic Diagram (Positive Logic)
SN74CBTLV3245A Simplified Schematic, Each FET SwitchSimplified Schematic, Each FET Switch