SN74CBTLV3245A

ACTIVE

3.3-V, 1:1 (SPST), 8-channel general-purpose FET bus switch

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3.3-V, 1:1 (SPST), 8-channel general-purpose FET bus switch

SN74CBTLV3245A

ACTIVE

Product details

Parameters

Configuration 1:1 SPST Number of channels (#) 8 Power supply voltage - single (V) 2.5, 3.3 Ron (Typ) (Ohms) 5 ON-state leakage current (Max) (µA) 60 Bandwidth (MHz) 200 Operating temperature range (C) -40 to 85 Features Powered-off protection Input/output continuous current (Max) (mA) 128 Rating Catalog open-in-new Find other Analog switches & muxes

Package | Pins | Size

SOIC (DW) 20 132 mm² 12.8 x 10.3 SSOP (DBQ) 20 52 mm² 8.65 x 6 TSSOP (PW) 20 42 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4 VQFN (RGY) 20 16 mm² 4.5 x 3.5 VQFN (RGY) 20 16 mm² 3.5 x 4.5 open-in-new Find other Analog switches & muxes

Features

  • Standard '245-Type Pinout
  • 5- Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

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Description

The SN74CBTLV3245A provides eight bits of high-speed bus switching in a standard '245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Datasheet SN74CBTLV3245A datasheet (Rev. M) May 23, 2005
Application notes Selecting the Right Texas Instruments Signal Switch (Rev. B) Apr. 02, 2020
Application notes Multiplexers and Signal Switches Glossary Mar. 06, 2020
Technical articles Roll with the design punches and overcome power-sequencing challenges Jul. 29, 2019
Application notes Eliminate power Sequencing with powered-off protection signal switches (Rev. B) Jan. 15, 2019
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Digital Bus Switch Selection Guide (Rev. A) Nov. 10, 2004
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Bus FET Switch Solutions for Live Insertion Applications Feb. 07, 2003
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
User guides CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) Dec. 01, 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

INTERFACE ADAPTERS Download
document-generic User guide
10
Description

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Features
  • Quick testing of TI's leaded surface mount packages 
  • Allows leaded suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 8 most popular leaded packages with a single panel


Design tools & simulation

SIMULATION MODELS Download
SCDM025B.ZIP (29 KB) - IBIS Model
SIMULATION MODELS Download
SCEJ235.ZIP (104 KB) - HSpice Model

Reference designs

REFERENCE DESIGNS Download
EtherCAT Interface for High Performance MCU Reference Design
TIDM-DELFINO-ETHERCAT — This reference design demonstrates how to connect a C2000 Delfino MCU to an EtherCAT™ ET1100 slave controller. The interface supports both demultiplexed address/data busses for maximum bandwidth and minimum latency and a SPI mode for low pin-count EtherCAT communication.  The slave (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
SOIC (DW) 20 View options
SSOP (DBQ) 20 View options
TSSOP (PW) 20 View options
TVSOP (DGV) 20 View options
VQFN (RGY) 20 View options

Ordering & quality

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