SN74CBTLV3245A

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Product details

Configuration 1:1 SPST Number of channels (#) 8 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (Typ) (Ohms) 5 ON-state leakage current (Max) (µA) 60 Bandwidth (MHz) 200 Operating temperature range (C) -40 to 85 Features Powered-off protection Input/output continuous current (Max) (mA) 128 Rating Catalog
Configuration 1:1 SPST Number of channels (#) 8 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (Typ) (Ohms) 5 ON-state leakage current (Max) (µA) 60 Bandwidth (MHz) 200 Operating temperature range (C) -40 to 85 Features Powered-off protection Input/output continuous current (Max) (mA) 128 Rating Catalog
SOIC (DW) 20 132 mm² 12.8 x 10.3 SSOP (DBQ) 20 52 mm² 8.65 x 6 TSSOP (PW) 20 29 mm² 4.4 x 6.5 TSSOP (PW) 20 29 mm² 6.5 x 4.4 TVSOP (DGV) 20 32 mm² 5 x 6.4 VQFN (RGY) 20 16 mm² 3.5 x 4.5 VQFN (RGY) 20 16 mm² 4.5 x 3.5
  • Standard '245-Type Pinout
  • 5- Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

  • Standard '245-Type Pinout
  • 5- Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

The SN74CBTLV3245A provides eight bits of high-speed bus switching in a standard '245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3245A provides eight bits of high-speed bus switching in a standard '245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Data sheet SN74CBTLV3245A datasheet (Rev. M) 23 May 2005
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. D) 09 Dec 2021
Application note Multiplexers and Signal Switches Glossary (Rev. B) 01 Dec 2021
Application note Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) 06 Jan 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Digital Bus Switch Selection Guide (Rev. A) 10 Nov 2004
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note Bus FET Switch Solutions for Live Insertion Applications 07 Feb 2003
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 01 Dec 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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Simulation model

SN74CBTLV3245A IBIS Model (Rev. B)

SCDM025B.ZIP (29 KB) - IBIS Model
Simulation model

HSPICE MODEL OF SN74CBTLV3245A

SCEJ235.ZIP (104 KB) - HSpice Model
Reference designs

TIDM-DELFINO-ETHERCAT — EtherCAT Interface for High Performance MCU Reference Design

This reference design demonstrates how to connect a C2000 Delfino MCU to an EtherCAT™ ET1100 slave controller. The interface supports both demultiplexed address/data busses for maximum bandwidth and minimum latency and a SPI mode for low pin-count EtherCAT communication.  The slave (...)
Package Pins Download
SOIC (DW) 20 View options
SSOP (DBQ) 20 View options
TSSOP (PW) 20 View options
TVSOP (DGV) 20 View options
VQFN (RGY) 20 View options

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