SCDS113F December   2002  – September 2026 SN74CB3Q3306A

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configuration and Functions
  5. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 ESD Ratings
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics
  6. 5Parameter Measurement Information
  7. 6Detailed Description
    1. 6.1 Functional Block Diagram
    2. 6.2 Device Functional Modes
  8. 7Device and Documentation Support
    1. 7.1 Documentation Support
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

2 Description

The SN74CB3Q3306A device is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3306A device provides an optimized interface option appropriate for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q3306A device is organized as two 1-bit switches with separate output-enable (1 OE, 2 OE) inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

The SN74CB3Q3306A device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To confirm the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Package Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN74CB3Q3306A VSSOP (8) 2.00mm × 3.10mm
TSSOP (8) 3.00mm × 6.10mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
SN74CB3Q3306A Simplified Schematic, Each FET Switch (SW) Simplified Schematic, Each FET Switch (SW)