SCDS141E October   2003  – September 2026 SN74CB3Q3305

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

1 Features

  • High-bandwidth data path (up to 500MHz)
  • 5V tolerant I/Os with device powered up or powered down
  • Low and flat ON-state resistance (ron) characteristics over operating range
    (ron = 3Ω typical)
  • Supports input voltage beyond supply on data I/O ports
    • 0 to 5V switching with 3.3V VCC
    • 0 to 3.3V switching with 2.5V VCC
  • Bidirectional data flow with near-zero propagation delay
  • Low input or output capacitance minimizes loading and signal distortion
    (Cio(OFF) = 3.5pF typical)
  • Fast switching frequency (fOE = 20MHz maximum)
  • Data and control inputs provide undershoot clamp diodes
  • Low power consumption (ICC = 0.25mA typical)
  • VCC operating range from 2.3V to 3.6V
  • Data I/Os support 0 to 5V signaling levels (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, and 5V)
  • Control inputs can be driven by TTL or
    5V/3.3V CMOS outputs
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II