SCEA047B November   2013  – November 2022 SN74LV1T00 , SN74LV1T02 , SN74LV1T04 , SN74LV1T08 , SN74LV1T32 , SN74LV1T86

 

  1.   No Title
  2. 1Advantages of Using the LVxT Gates and Buffers to Translate
  3. 2Translating Down
  4. 3Translating Up
  5. 4Example Application 1: PWM with Filter
  6. 5Example Application 2: PGOOD Circuit
  7. 6Conclusion
  8. 7Revision History

Translating Up

Using the LVxT family to translate up is very simple. The input switching threshold is lowered, thus the high state voltage level (VIH) of the input can be much lower than that used for a typical CMOS device. For example, if the VCC is 3.3 V, the typical CMOS switching threshold would be VCC/2, or 1.65 V. Thus the input high voltage level (VIH) must be at least VCC × 0.7, or 2.31 V. However, for LVxT devices the input threshold for 3.3-V VCC is approximately 1 V. This allows a signal with a 1.8-V VIH to be translated up to the VCC level of 3.3 V. See an example of this in the voltage characteristic plot, Figure 1.

Common up translation possibilities with LVxT family:

  • 2.5-V VCC: from 1.8 V to 2.5 V
  • 3.3-V VCC: from 1.8 V or 2.5 V to 3.3 V
  • 5-V VCC: from 2.5 V or 3.3 V to 5 V

Because these parts are CMOS, there is additional supply current (ICC) consumption only when the input is much less than VCC, which is common when up-translating. The current draw for up-translation at different input values is shown in Figure 2-2.