SCES584D June   2005  – May 2026 SN74LVC8T245

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information DB, DBQ and DGV
    5. 5.5  Thermal Information PW and RHL
    6. 5.6  Electrical Characteristics
    7. 5.7  Switching Characteristics, VCCA = 1.8V ± 0.15V
    8. 5.8  Switching Characteristics, VCCA = 2.5V ± 0.2V
    9. 5.9  Switching Characteristics, VCCA = 3.3V ± 0.3V
    10. 5.10 Switching Characteristics, VCCA = 5V ± 0.5V
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65V to 5.5V Power-Supply Range
      2. 7.3.2 Ioff Supports Partial-Power-Down Mode Operation
      3. 7.3.3 Glitch-free Power Supply Sequencing
      4. 7.3.4 Balanced High-Drive CMOS Push-Pull Outputs
      5. 7.3.5 VCC Isolation and VCC Disconnect
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

1 Features

  • Fully configurable dual-rail design allows each port to operate over the full 1.65V to 5.5V power-supply range
  • Robust, glitch-free power supply sequencing
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • VCC isolation feature and VCC disconnect feature
    • if either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high- impedance state
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • Operating temperature from -40°C to 85°C
  • ESD protection exceeds JESD 22
    • 4000V Human-Body Model (A114-A)
    • 1000V Charged-Device Model (C101)