8-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and Three-State Outputs
Product details
Parameters
Package | Pins | Size
Features
- Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
- VCC Isolation Feature – If Either VCC Input Is at GND, All Are in the High-Impedance State
- Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 4000-V Human-Body Model (A114-A)
- 100-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Description
This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245 is optimized to operate with VCCA and VCCB set at 1.65 V to 5.5 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.
The SN74LVC8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74LVC8T245 is designed so that the control pins (DIR and OE) are supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, all outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic and translation devices with included dual supply support
- Board has 9 sections that can be broken apart for a smaller form factor
Description
The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC is (...)
Features
- SMB connector available for high speed operation
- Ground port available on each header pin to maintain signal integrity
- DIR and OE have 10K ohm pull up /pull down resistor options
- Designed to support up to 20 different devices
Design tools & simulation
Reference designs
Design files
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download Multi-Protocol Position Encoder Interface With AM437x on PRU-ICSS BOM.pdf (79KB) -
download Multi-Protocol Position Encoder Interface With AM437x on PRU-ICSS Assembly Files.zip (54KB) -
download Multi-Protocol Position Encoder Interface With AM437x on PRU-ICSS Layer Plots.zip (217KB) -
download Multi-Protocol Position Encoder Interface With AM437x on PRU-ICSS PCB 3D PRINT.zip (3301KB) -
download Multi-Protocol Position Encoder Interface With AM437x on PRU-ICSS CAD Files.zip (666KB) -
download Multi-Protocol Position Encoder Interface With AM437x on PRU-ICSS Gerber .zip (473KB)
Design files
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download AM437x/AMIC120 Industrial Development Kit (IDK) Gerber Files (Rev. A).zip (11389KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Assembly Drawing Files (Rev. A).zip (870KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Design Files (CAD) (Rev. A).zip (21148KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Layer Plots (Rev. A).zip (6065KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Bill of Materials (BOM) (Rev. A).zip (580KB)
Design files
Design files
Design files
-
download AM437x/AMIC120 Industrial Development Kit (IDK) Gerber Files (Rev. A).zip (11389KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Assembly Drawing Files (Rev. A).zip (870KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Design Files (CAD) (Rev. A).zip (21148KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Layer Plots (Rev. A).zip (6065KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Bill of Materials (BOM) (Rev. A).zip (580KB)
Design files
-
download EnDAT 2.2 System BOM.pdf (119KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Gerber Files (Rev. A).zip (11389KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Assembly Drawing Files (Rev. A).zip (870KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Design Files (CAD) (Rev. A).zip (21148KB) -
download AM437x/AMIC120 Industrial Development Kit (IDK) Layer Plots (Rev. A).zip (6065KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SO (NS) | 24 | View options |
SOIC (DW) | 24 | View options |
SSOP (DB) | 24 | View options |
SSOP (DBQ) | 24 | View options |
TSSOP (PW) | 24 | View options |
TVSOP (DGV) | 24 | View options |
VQFN (RHL) | 24 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
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