Home Logic Voltage level translators Direction-controlled voltage translators

SN74LVC8T245

ACTIVE
Order now

8-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and Three-State Outputs

Data sheet
Top
8-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and Three-State Outputs

SN74LVC8T245

ACTIVE
Data sheet Order now

Product details

Parameters

Technology Family LVC Applications GPIO Bits (#) 8 High input voltage (Min) (Vih) 1.08 High input voltage (Max) (Vih) 5.5 Output voltage (Min) (V) 1.65 Output voltage (Max) (V) 5.5 IOH (Max) (mA) -32 IOL (Max) (mA) 32 Rating Catalog open-in-new Find other Direction-controlled voltage translators

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 SOP (NS) 24 117 mm² 15 x 7.8 SSOP (DB) 24 64 mm² 8.2 x 7.8 SSOP (DBQ) 24 52 mm² 8.65 x 6 TSSOP (PW) 24 34 mm² 4.4 x 7.8 TVSOP (DGV) 24 32 mm² 5 x 6.4 VQFN (RHL) 24 19 mm² 3.5 x 5.5 open-in-new Find other Direction-controlled voltage translators

Features

  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Are in the High-Impedance State
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 100-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
 open-in-new Find other Direction-controlled voltage translators

Description

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245 is optimized to operate with VCCA and VCCB set at 1.65 V to 5.5 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.

The SN74LVC8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC8T245 is designed so that the control pins (DIR and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, all outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

 open-in-new Find other Direction-controlled voltage translators
Download

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 33
Type Title Date
* Datasheet SN74LVC8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs datasheet (Rev. B) Nov. 26, 2014
Selection guides Voltage translation buying guide Jun. 13, 2019
User guides Generic AVC and LVC Direction Controlled Translation EVM (Rev. A) Feb. 18, 2019
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
User guides Generic AVC and LVC Direction Controlled Translation EVM May 09, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Designing with SN74LVCXT245 and SN74LVCHXT245 Family of Direction Controlled Oct. 27, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application notes Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature Military Low Voltage Solutions Apr. 04, 2001
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes LVC Characterization Information Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
User guides Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details
EVALUATION BOARDS Download
document-generic User guide
149
Description

The ADC1175-50 evaluation module (EVM) is used to evaluate the ADC1175-50 8-bit, 50-MSPS analog-to-digital converter (ADC). The EVM has a single-ended, DC-coupled analog input to accommodate the ADC1175-50 full-scale sampling range. The ADC1175-50EVM is designed to connect directly to a variety of (...)

Features
  • Clocking provided by onboard crystal or external source
  • 40-pin header connects directly to TSW1400EVM and TSW1405EVM data-capture solution via CMOS interface
  • High-Speed Data Converter Pro Software (DATACONVERTERPRO-SW) analysis tool provides complete environment for signal analysis, including data (...)
View details
EVALUATION BOARDS Download
document-generic User guide
20
Description

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC is (...)

Features
  • SMB connector available for high speed operation
  • Ground port available on each header pin to maintain signal integrity
  • DIR and OE have 10K ohm pull up /pull down resistor options
  • Designed to support up to 20 different devices
View details
EVALUATION BOARDS Download
document-generic User guide
199
Description
This EVM provides the user with the ability to evaluate the TL16C750E device and its features. The EVM includes an onboard 3.3-V LDO as well as level translation for processors which operate at a higher voltage rail.
Features
  • Fractional baudrate support
  • 128-byte FIFO depth
View details

Software development

PLUG-INS Download
ADC1175 8-Bit 20MSPS Analog-to-Digital Converter (ADC) Evaluation Module
ADC1175EVM — The ADC1175 evaluation module (EVM) is used to evaluate the ADC1175 8-bit, 20-MSPS analog-to-digital converter (ADC). The EVM has a single-ended, DC-coupled analog input to accommodate the ADC1175 full-scale sampling range. The ADC1175EVM is designed to connect directly to a variety of data-capture (...)
149
Features
  • Operational amplifier provides buffering and signal conditioning for DC-coupled input network
  • Clocking provided by onboard crystal or external source
  • 40-pin header connects directly to TSW1400EVM and TSW1405EVM data-capture solution via CMOS interface
  • High-Speed Data Converter Pro Software (...)
View details

Design tools & simulation

SIMULATION MODELS Download
SCEM494.ZIP (56 KB) - IBIS Model

Reference designs

REFERENCE DESIGNS Download
Multi-Protocol Digital Position Encoder Master Interface Reference Design With AM437x on PRU-ICSS
TIDEP0057 — TI provides the system solution for Industrial Communication on Sitara™ processors with Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS). This TI Design describes the integrated multi-protocol digital position encoder master interface support. The supported digital (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Single Chip Drive for Industrial Communications and Motor Control
TIDEP0025 — This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design
TIDEP0046 — TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design
TIDEP0047 — This TI Design (TIDEP0047) is a reference platform based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This TI Design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
ARM MPU with Integrated BiSS C Master Interface Reference Design
TIDEP0022 — Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design
TIDEP0035 — Implementation of HIPERFACE DSL Master protocol on Industrial Communication Sub-System (PRU-ICSS). The two wire interface allows for integration of position feedback wires into motor cable.  Complete solution consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
EnDat 2.2 System Reference Design
TIDEP0050 — The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
SO (NS) 24 View options
SOIC (DW) 24 View options
SSOP (DB) 24 View options
SSOP (DBQ) 24 View options
TSSOP (PW) 24 View options
TVSOP (DGV) 24 View options
VQFN (RHL) 24 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

View all topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Training series

View all TI training and videos

Videos

Related videos