SCES945A May   2022  – October 2025 CDCBT1001

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Down Tolerant Input
      2. 6.3.2 Up Conversion
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Processor Clock Up Translation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

3 Description

The CDCBT1001 is a 1.2V to 3.3V clock buffer and level translator. The VDD_IN pin supply voltage defines the input LVCMOS clock level. The VDD_OUT pin supply voltage defines the output LVCMOS clock level. VDD_IN = 1.2V, 1.8V, 2.5V, or 3.3V ± 10%. VDD_OUT = 1.2V, 1.8V, 2.5V, or 3.3V ± 10%.

The 12kHz to 5MHz additive RMS jitter at 24MHz is less than 0.8ps.

Package Information
PART NUMBERPACKAGE(1)PACKAGE SIZE(2)
CDCBT1001DPW (X2SON, 5)0.80mm × 0.80mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
CDCBT1001 Block DiagramBlock Diagram

CDCBT1001 Pin Configuration
Pin Configuration