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CDCBT1001

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1.2V to 3.3V clock buffer and level translator

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Data sheet

CDCBT1001

ACTIVE
Data sheet Order now

Product details

Number of outputs 1 Core supply voltage (V) 1.2, 1.8, 2.5, 3.3 Output supply voltage (V) 1.2, 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS Input type LVCMOS
Number of outputs 1 Core supply voltage (V) 1.2, 1.8, 2.5, 3.3 Output supply voltage (V) 1.2, 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS Input type LVCMOS
X2SON (DPW) 5 0.64 mm² (0.8 mm × 0.8 mm)
  • Low additive jitter and phase noise:
    • 0.8ps maximum 12kHz to 5MHz additive RMS jitter (fout = 24MHz)
    • –120dBc/Hz maximum phase noise at 1kHz offset (fout = 24MHz)
    • –148dBc/Hz maximum phase noise floor (fout = 24MHz, foffset ≥ 1MHz)
  • 5ns 20% to 80% rise/fall time
  • 10ns propagation delay
  • Low current consumption
  • –40°C to 85°C operating temperature range
  • Flexible output from operational frequency
  • Low additive jitter and phase noise:
    • 0.8ps maximum 12kHz to 5MHz additive RMS jitter (fout = 24MHz)
    • –120dBc/Hz maximum phase noise at 1kHz offset (fout = 24MHz)
    • –148dBc/Hz maximum phase noise floor (fout = 24MHz, foffset ≥ 1MHz)
  • 5ns 20% to 80% rise/fall time
  • 10ns propagation delay
  • Low current consumption
  • –40°C to 85°C operating temperature range
  • Flexible output from operational frequency

The CDCBT1001 is a 1.2V to 3.3V clock buffer and level translator. The VDD_IN pin supply voltage defines the input LVCMOS clock level. The VDD_OUT pin supply voltage defines the output LVCMOS clock level. VDD_IN = 1.2V, 1.8V, 2.5V, or 3.3V ± 10%. VDD_OUT = 1.2V, 1.8V, 2.5V, or 3.3V ± 10%.

The 12kHz to 5MHz additive RMS jitter at 24MHz is less than 0.8ps.

The CDCBT1001 is a 1.2V to 3.3V clock buffer and level translator. The VDD_IN pin supply voltage defines the input LVCMOS clock level. The VDD_OUT pin supply voltage defines the output LVCMOS clock level. VDD_IN = 1.2V, 1.8V, 2.5V, or 3.3V ± 10%. VDD_OUT = 1.2V, 1.8V, 2.5V, or 3.3V ± 10%.

The 12kHz to 5MHz additive RMS jitter at 24MHz is less than 0.8ps.
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Technical documentation

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* Data sheet CDCBT1001 1.2V to 3.3 V Clock Buffer and Level Translator datasheet (Rev. A) PDF | HTML Oct 24, 2025
Certificate CDCBT1001EVM EU RoHS Declaration of Conformity (DoC) Mar 25, 2022

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Simulation model

CDCBT1001 IBIS model

SCEM796.ZIP (13 KB) - IBIS model
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X2SON (DPW) 5 Ultra Librarian
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