SCES994 June   2025 TXGS441-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCCA = 1.8 ± 0.15V
    7. 5.7  Switching Characteristics, VCCA = 2.5 ± 0.2V
    8. 5.8  Switching Characteristics, VCCA = 3.3 ± 0.3V
    9. 5.9  Switching Characteristics, VCCA = 5.0 ± 0.5V
    10. 5.10 Switching Characteristics: Tsk, TMAX
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 7.3.1.1 Inputs with Integrated Static Pull-Down Resistors
      2. 7.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 7.3.3 VCC Disconnect
      4. 7.3.4 Over-Voltage Tolerant Inputs
      5. 7.3.5 Glitch-Free Power Supply Sequencing
      6. 7.3.6 Negative Clamping Diodes
      7. 7.3.7 Fully Configurable Dual-Rail Design
      8. 7.3.8 Supports High-Speed Translation
      9. 7.3.9 AC Noise Rejection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, generators supply all input pulses that have the following characteristics:

  • f = 1MHz
  • ZO = 50Ω
  • Δt/ΔV ≤ 1ns/V
TXGS441-SEP Load Circuit
A. CL includes probe and jig capacitance.
Figure 6-1 Load Circuit
Table 6-1 Load Circuit Conditions
ParameterVCCORLCLS1VTP
tpdPropagation (delay) time1.71V – 5.5V10kΩ15pFOpenN/A
ten, tdisEnable time, disable time1.71V – 2.7V10kΩ15pF2 × VCCO0.15V
3.0V – 5.5V10kΩ15pF2 × VCCO0.3V
ten, tdisEnable time, disable time1.71V – 2.7V10kΩ15pFGND0.15V
3.0V – 5.5V10kΩ15pFGND0.3V
TXGS441-SEP Switching Characteristics Voltage Waveforms
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 6-2 Switching Characteristics Voltage Waveforms
TXGS441-SEP Default Output Delay Time & Time from UVLO to Valid Output Voltage Waveform
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 6-3 Default Output Delay Time & Time from UVLO to Valid Output Voltage Waveform
TXGS441-SEP Enable Time And Disable Time
  1. Output waveform on the condition that input is driven to a valid Logic Low.
  2. Output waveform on the condition that input is driven to a valid Logic High.
  3. VCCO is the supply pin associated with the output port.
  4. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 6-4 Enable Time And Disable Time
TXGS441-SEP Common-Mode Transient Immunity Test Circuit
  1. CL = 15pF and includes instrumentation and fixture capacitance within ±20%.
Figure 6-5 Common-Mode Transient Immunity Test Circuit