In this design, a pre-defined message is going to be show in a 16x6 graphic display, this means that such information needs to be saved somewhere inside the TPLD device. Additionally, each of the rows must be activated one at time, so, a synchrony system must also be included to keep control of the internal elements in this device as well as the external TPLD column's controllers.

Regarding the data that can be displayed, a 16-states finite state machine can be a good way to generate each of the values at time required for each of the rows of the dot-matrix display. The TPLD1202 includes an 8-states FSM built-in in hardware, so 16-states FSM can be implemented using this FSM plus a secondary FSM built with true – tables and D flip-flops. In addition, the secondary FSM can also generate the synchronization signal required.

Figure 2-1 shows the message that can be displayed and the row data involved as well. Notice that the left section is handled by the FSM and the right one is handled by the sequencer plus LUTs as well.