SCLA079 April   2025 TPLD1202

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Implementing the Multiplexing Display Controller in TPLD
    1. 2.1 Data and Synchronization Generator
    2. 2.2 Configuring the FSM in Interconnect Studio
    3. 2.3 Configuring TYPE-D Flip-Flops (DFF) in Interconnect Studio
    4. 2.4 Configuring the True – Tables in Interconnect Studio
    5. 2.5 Configuring the Oscillator in Interconnect Studio
  6. 3Summary
  7. 4References

Configuring TYPE-D Flip-Flops (DFF) in Interconnect Studio

The next section of the Multiplexed display’s data generator can be implemented with a classical Moore FSM including next-state logic, memory an output logic section. But, because the FSM is going to run all the time form ST0 to ST7, we can implement a count-down counter with DFF saving the next-state logic in some kind of sequencer. So finally, we can add the output logic based on true – tables fashion, and implemented in LUTs macrocells in order to generate the given data needed accordingly to the state of the sequencer, as is shown in the Figure 2-4. Regarding the sequencer, the same figure is showing how a DFF can be defined to operate as Toggle FF, and therefore, all TFFs working together as a countdown counter.

 Countdown Counter Implemented
                    With T-FFs Figure 2-4 Countdown Counter Implemented With T-FFs