SCPA074 September 2024 TPLD1202
Figure 3-1 PGEN With Reset (10-bit Pattern, 0x1F2) Example Configuration in ICS
Figure 3-2 Logic Analyzer Capture of PGEN With Reset (10-bit Pattern, 0x1F2)
Figure 3-3 Logic Analyzer Capture of PGEN With Reset (10-bit Pattern, 0x1F2, Zoomed)