SCPS277C November   2022  â€“ January 2025 TCAL6408

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 I2C Bus Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Translation
      2. 7.3.2 I/O Port
      3. 7.3.3 Adjustable Output Drive Strength
      4. 7.3.4 Interrupt Output (INT)
      5. 7.3.5 Reset Input (RESET)
      6. 7.3.6 Software Reset Call
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
    6. 7.6 Register Maps
      1. 7.6.1 Device Address
      2. 7.6.2 Control Register and Command Byte
      3. 7.6.3 Register Descriptions
      4. 7.6.4 Bus Transactions
        1. 7.6.4.1 Writes
        2. 7.6.4.2 Reads
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Minimizing ICC When I/Os Control LEDs
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus controller sends a command byte, which is stored in the control register in the TCAL6408. The lower two bits of this data byte reflect the internal registers (input, output, polarity inversion, or configuration) that are affected. Bit 6 in conjunction with the lower four bits of the Command byte are used to point to the extended features of the device (Agile IO). The command byte is sent only during a write transmission.

Once a new command has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. Upon power-up, hardware reset, or software reset, the control register defaults to 00h.

TCAL6408 Control Register BitsFigure 7-8 Control Register Bits
Table 7-4 Command Byte
CONTROL REGISTER BITSCOMMAND BYTE
(HEX)
REGISTERPROTOCOLPOWER-UP
DEFAULT
B7B6B5B4B3B2B1B0
0000000000Input PortRead bytexxxx xxxx
0000000101Output PortRead/write byte1111 1111
0000001002Polarity InversionRead/write byte0000 0000
0000001103ConfigurationRead/write byte1111 1111
0100000040Output Drive Strength 0Read/write byte1111 1111
0100000141Output Drive Strength 1Read/write byte1111 1111
0100001042Input latch registerRead/write byte0000 0000
0100001143Pull-up/pull-down enable registerRead/write byte0000 0000
0100010044pull-up/pull-down selection registerRead/write byte1111 1111
0100010145Interrupt mask registerRead/write byte1111 1111
0100011046Interrupt status registerRead byte0000 0000
010011114FOutput port configuration registerRead/write byte0000 0000