SCPS314 December   2025 TCA9536-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 I2C Bus Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 P3 or Interrupt (INT) Output
      3. 7.3.3 Pull-up Disable Functionality
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Powered-Up
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 Writes
        2. 7.5.1.2 Reads
      2. 7.5.2 Software Reset Call
    6. 7.6 Register Maps
      1. 7.6.1 Device Address
      2. 7.6.2 Control Register and Command Byte
      3. 7.6.3 Register Descriptions
  9. 8 Application Information
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
        1. 8.1.1.1 Minimizing ICC When I/Os Control LEDs
      2. 8.1.2 Detailed Design Procedure
      3. 8.1.3 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 Power-On Reset
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

9.1 Power-On Reset

In the event of a glitch or data corruption, the TCA9536-Q1 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in and Figure 9-1.

TCA9536-Q1 VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCCFigure 9-1 VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC

Table 9-1 specifies the performance of the power-on reset feature for the device for both types of power-on reset.

Table 9-1 Recommended Supply Sequencing And Ramp Rates
PARAMETER(1)MINMAXUNIT
VCC_FTFall rateSee Figure 9-11ms
VCC_RTRise rateSee Figure 9-10.1ms
VCC_TRRTime to re-ramp (when VCC drops to VPOR_MIN – 50mV or when VCC drops to GND)See Figure 9-12μs
VCC_GHLevel that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1µsSee Figure 9-21.2V
VCC_GWGlitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCC (For VCC > 3V)See Figure 9-210μs
(1) All supply sequencing and ramp rate values are measured at TA = 25°C

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 9-2 and Table 9-1 provide more information on how to measure these specifications.

TCA9536-Q1 Glitch Width and Glitch HeightFigure 9-2 Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 9-3 and Table 9-1 provide more details on this specification.

TCA9536-Q1 VPORFigure 9-3 VPOR