SCPS317 June   2026 TXE8148

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Bus Hold
      5. 7.3.5 Fail-safe Mode
      6. 7.3.6 Software Reset Call
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Feature Register Mapping
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Burst Mode
      4. 7.5.4 SPI Write
      5. 7.5.5 SPI Read
      6. 7.5.6 SPI Daisy Chain
    6. 7.6 TXE8148 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TXE8148 DGG (TSSOP) Package, 56-Pin(Top View) Figure 4-1 DGG (TSSOP) Package, 56-Pin
(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME TSSOP
(DGG)
INT 1 O Interrupt output. Connect to VCC through a pullup resistor.
RESET/FAIL-SAFE 2 I Active Low reset input. Connect to VCC through a pullup resistor.
GND 3 G Ground
VCC 4 P Supply voltage
P1.0 5 I/O P-port input/output. At power on, Port 1 - IO #0 is configured as an input.
P1.1 6 I/O P-port input/output. At power on, Port 1 - IO #1 is configured as an input.
P1.2 7 I/O P-port input/output. At power on, Port 1 - IO #2 is configured as an input.
P1.3 8 I/O P-port input/output. At power on, Port 1 - IO #3 is configured as an input.
P1.4 9 I/O P-port input/output. At power on, Port 1 - IO #4 is configured as an input.
P1.5 10 I/O P-port input/output. At power on, Port 1 - IO #5 is configured as an input
P1.6 11 I/O P-port input/output. At power on, Port 1 - IO #6 is configured as an input.
P1.7 12 I/O P-port input/output. At power on, Port 1 - IO #7 is configured as an input.
P2.0 13 I/O P-port input/output. At power on, Port 2 - IO #0 is configured as an input.
P2.1 14 I/O P-port input/output. At power on, Port 2 - IO #1 is configured as an input.
P2.2 15 I/O P-port input/output. At power on, Port 2 - IO #2 is configured as an input.
P2.3 16 I/O P-port input/output. At power on, Port 2 - IO #3 is configured as an input.
P2.4 17 I/O P-port input/output. At power on, Port 2 - IO #4 is configured as an input.
P2.5 18 I/O P-port input/output. At power on, Port 2 - IO #5 is configured as an input.
P2.6 19 I/O P-port input/output. At power on, Port 2 - IO #6 is configured as an input.
P2.7 20 I/O P-port input/output. At power on, Port 2 - IO #7 is configured as an input.
P3.0 21 I/O P-port input/output. At power on, Port 3 - IO #0 is configured as an input.
P3.1 22 I/O P-port input/output. At power on, Port 3 - IO #1 is configured as an input
P3.2 23 I/O P-port input/output. At power on, Port 3 - IO #2 is configured as an input.
P3.3 24 I/O P-port input/output. At power on, Port 3 - IO #3 is configured as an input.
P3.4 25 I/O P-port input/output. At power on, Port 3 - IO #4 is configured as an input.
P3.5 26 I/O P-port input/output. At power on, Port 3 - IO #5 is configured as an input.
P3.6 27 I/O P-port input/output. At power on, Port 3 - IO #6 is configured as an input.
P3.7 28 I/O P-port input/output. At power on, Port 3 - IO #7 is configured as an input.
P5.0 29 I/O P-port input/output. At power on, Port 5 - IO #0 is configured as an input.
P5.1 30 I/O P-port input/output. At power on, Port 5 - IO #1 is configured as an input.
P5.2 31 I/O P-port input/output .At power on, Port 5 - IO #2 is configured as an input.
P5.3 32 I/O P-port input/output. At power on, Port 5 - IO #3 is configured as an input.
P5.4 33 I/O P-port input/output. At power on, Port 5 - IO #4 is configured as an input.
P5.5 34 I/O P-port input/output. At power on, Port 5 - IO #5 is configured as an input.
P5.6 35 I/O P-port input/output. At power on, Port 5 - IO #6 is configured as an input.
P5.7 36 I/O P-port input/output. At power on, Port 5 - IO #7 is configured as an input
P4.0 37 I/O P-port input/output. At power on, Port 4 - IO #0 is configured as an input
P4.1 38 I/O P-port input/output. At power on, Port 4 - IO #1 is configured as an input
P4.2 39 I/O P-port input/output. At power on, Port 4 - IO #2 is configured as an input
P4.3 40 I/O P-port input/output. At power on, Port 4 - IO #3 is configured as an input
P4.4 41 I/O P-port input/output. At power on, Port 4 - IO #4 is configured as an input
P4.5 42 I/O P-port input/output. At power on, Port 4 - IO #5 is configured as an input
P4.6 43 I/O P-port input/output. At power on, Port 4 - IO #6 is configured as an input
P4.7 44 I/O P-port input/output. At power on, Port 4 - IO #7 is configured as an input
P0.0 45 I/O P-port input/output. At power on, Port 0 - IO #0 is configured as an input
P0.1 46 I/O P-port input/output. At power on, Port 0 - IO #1 is configured as an input
P0.2 47 I/O P-port input/output. At power on, Port 0 - IO #2 is configured as an input
P0.3 48 I/O P-port input/output. At power on, Port 0 - IO #3 is configured as an input.
P0.4 49 I/O P-port input/output. At power on, Port 0 - IO #4 is configured as an input.
P0.5 50 I/O P-port input/output. At power on, Port 0 - IO #5 is configured as an input.
P0.6 51 I/O P-port input/output. At power on, Port 0 - IO #6 is configured as an input.
P0.7 52 I/O P-port input/output. At power on, Port 0 - IO #7 is configured as an input.
CS 53 I SPI chip select input. Internal pullup resistor.
SCLK 54 I SPI serial clock input. Internal pulldown resistor.
SDI 55 I SPI serial data input.
SDO 56 O SPI serial data output. Push-pull output
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power