2 Simulation and Best Layout Practices

To illustrate the impact of layout on total voltage drop across the shunts, three TINA-TI simulations were performed, representing different design approaches. The following section details the effect of trace geometry and shunt placement on the overall effective shunt voltage.

Three shunt resistor values - 270µΩ, 300µΩ and 330µΩ - were used across the designs. The 10% variation in these values simulate the worst-case tolerance and resistance variations encountered in practical applications. Resistors in µΩ range were specifically chosen to maximize the impact of auxiliary resistances, as their impedance is comparable to that of the shunt.

The following is a list of the components and configuration-details of the TINA-TI simulation (Fig 2-1):

• All three approaches have 20A current flowing across the shunts
• R_{solder_SR} and R_{solder_ST} represent the solder resistance between shunt - resistor pad and shunt - trace respectively
• R_cu and R_trace are the simulation resistances between shunts due to the copper layer
• Current sources (Ib) above the output voltage represent the input bias current of the INA190 (3nA)
• R_cu(TL), R_cu(TR), R_cu(BL), R_cu(BR) represent the resistances associated with the surface mount spade connectors
• Voltage-controlled voltage source is used to simulate the INA190's ideal gain stage and is set to 200 V/V

The trace resistances (10m, 20m, 30m) are length-dependent approximates based on trace resistivity calculations from the Saturn PCB Design Toolkit. The copper resistance is based on the concept that sheet resistance of 1 ounce copper is 500µΩ/square. There are a total of two spade connectors on either side of the shunts Figure 5-4 through which current is supplied to the circuit, hence there are five connections possible, for example. Top-Right to Bottom-Right (TR-BR), Top-Right to Bottom-Left (TR-BL), Top-Left to Bottom-Right (TL-BR), Top-Left to Bottom-Left (TL-BL) and both together (TR,TL to BR,BL).

In a complex resistor network (Figure 5-5), the total resistance encountered by the current is highly dependent on the specific path taken. Table 2-1 lists simulation results from Layout 2 and 3, with the current path in different combinations.

From Table 2-1, deduce that the best possible combinations for current flow are TL - BR, TR-BL or Both - Both. Figure 5-5 in the supplementary section depicts how the simulation's resistor network was designed for the PCB layout.

All three layouts utilize the established Kelvin sensing principle, particularly since it is most critical for accuracy with low-value shunt resistors. Moreover, with Rshunts of 270µΩ, 300µΩ and 330µΩ in parallel, the effective resistance is 99.3311 (Reffective = 1/((1/270u) + (1/300u) + (1/330u)), and hence expected V_out is 397.32mV (99.3311µΩ x 20A x 200V/V). The following three layouts attempt to get as close as possible to the expected value.

In Figure 2-1, the sense traces are designed to connect to the shunt closest to the device. Since the sense traces are tapping the shunt resistors from further down the high-current path, this includes the voltage drop across solder joints and traces in the effective shunt voltage drop.

This is an example of a bad layout because it deliberately introduces the maximum amount of unwanted, external parasitic resistances into the differential measurement path, leading to maximum output voltage offset (56.47mV) i.e. largest difference between measured Vout and expected Vout.

Layout 2 has Kelvin connections setup to the shunt in the middle. There are lower-resistance parallel paths for current to flow through as opposed to through the middle shunt, hence the current through the middle shunt is comparatively less (5.77A). In addition, since the copper layer provides many alternative paths for current to flow through instead of through the shunt, there will be a significant voltage drop in the PCB's copper layer - greater than the voltage drop across shunt.

Thus kelvin sensing from the centre-shunt leads to a output voltage offset of 51.22mV.

Layout 3 is considered the best layout practice because it has Kelvin connections from each shunt resistor. Individual Kelvin sensing lines minimize the effect of parasitic resistance of trace and solder on the total effective shunt voltage. It also accounts for all three shunt voltage drops, hence you can get an accurate output regardless of how current is split between the resistors.

Moreover, when multiple Kelvin connections are used, the traces can inadvertently form low impedance loops, providing a path for the circulation of undesired currents. Therefore, to mitigate this issue and maintain measurement integrity, current-limiting resistors that are at least 100 times greater than the shunt resistors are incorporated in series with the Kelvin traces. Without these resistors hundreds of milliamps of current is circulating in the Kelvin traces, generating detrimental heat. If greater circulating current suppression is required, use a larger limiting resistor as depicted in the layout. These resistors also enable averaging of the voltage across each shunt, hence improving accuracy. Note, the current-limiting resistors may cause error in devices with higher input bias currents.

In summary, this the best layout practice since the effective voltage drop across the shunts measured at VM4 is the closest to the calculated value of 397.32mV.