SDAA115 November   2025 INA190

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Simulation and Best Layout Practices
  6. 3Results
  7. 4Summary
  8. 5Supplementary
  9. 6References

4 Summary

This paper has discussed the challenges and high susceptibility of low-ohmic shunts to parasitic effects such as PCB trace, solder and copper plane resistance. To mitigate these issues, this paper has also discussed variations across three PCB layouts through TINA-TI simulations and bench-test data, which show similar trends. Layout 1 is has the greatest output voltage offset in simulations, but Layout 2's measured output offset is larger. This could be attributed to smaller solder resistances and shunt resistance variations. Layout 1 and 2's measured Vout mirror the simulation results. Finally, Layout 3 is proved to be the most robust and effective since it has the smallest Vout offset, as seen in both simulation and bench-testing.