6 Extending the Timer for Cyclic Wake Ups with External Components

Cyclic wake up has many advantages when used in a system and there are clear reasons why a user wants to use cyclic wake up. Currently, implementations of the cyclic timer on TI SBCs have a maximum timer period of 2s. In many use cases the maximum period of 2s is sufficient. However, imagine a system that is in a low power sleep mode where the main power is derived from a battery. Current consumption is critical in these types of applications and every time the device is woken up by the cyclic timer there is an increase in supply current due to the mode transition into a higher power operational mode. With current consumption in mind, assume the system is in a low power mode for hours at a time. If power usage spikes every 2 seconds a user can see a negative impact on battery power over time. Generally, the alternative choice in these designs is to increase the wake timer period beyond 2 seconds. Having a longer timer period reduces the overall current consumption by reducing the polling of the device in sleep mode To increase the wake timer period for TCAN24xx-Q1 or TCAN28xx-Q1 or any TI SBC device that has limited options for timer period configurations but also has local wake up pins available, an external design can be used.

At first glance, the design to this system requirement seems simple: the internal SBC timer is not long enough, so an external timer must be used. The external timer can have the output connected to a local SBC WAKE pin to achieve the goal of a longer period for the wake timer. In this type of application, the SBC is in sleep mode and all the integrated regulators to the SBC are off, so the external timer cannot be powered by the SBC during this time. This means that the timer must be powered off battery, which is typically 12V in automotive systems, while the SBC can withstand up to 28V. Select an external timer with similar considerations. Based on the input voltage requirement, a 555 timer device such as the TLC3555-Q1 can be a fit.

Figure 6-1 Extended Cyclic Wake Timer Using 555 Timer

This design is based off a classic 555 timer in an a stable configuration that can be tuned using simple RC components. When the SBC is awake the VCC1 output turns on the NMOS and put the timer into reset (forcing output low); so during normal operation the 555 timer is in reset. When the SBC goes to sleep,VCC1 is off and the 555 timer begins to send a pulse on the OUT pin based on the RC configuration of the circuit. This output pulse from the 555 timer can exceed the 2s max on the internal SBC timer. Switch the wake pin to only look for either low – high – low pulse or low to high transitions. By default, many SBCs are edge detection.

There are two design considerations when taking this approach. The first being that the TLC3555-Q1 can only withstand up to 20V on the supply input before the device can be damaged. In 12V automotive systems this is generally not enough for common transients as to why TI’s SBCs are rated to 28V. The second reason related to low power design. A common requirement in many automotive applications is that the sleep current is less than 100uA. The TLC3555-Q1 sleep current at 12V input is going to be between 240uA to 310uA worst case This leaves no room in the 100uA limit, if the 100uA limit is a system requirement. If 100uA sleep current is required, there is a way around this issue.

Figure 6-2 Low Power Extended Cyclic Wake Timer Implementation on TI SBCs

The adjusted design is more complex, but the basic idea is similar to the previous idea. When the SBC goes into sleep mode, the timer starts sending pulses to the wake pin based on the timers RC configuration. To achieve lower power, a lower input voltage timer must be used such as the TPL5110-Q1. Since this is a 5V timer the 12V nominal system input needs to be regulated to 5V – to generate a 5V rail an LDO (the TPS7B81-Q1) can be used while the rest of the system is in sleep mode. However, based on the circuit diagram, there are a few more design considerations to make. R3 is used to set the interval period, which can be between 100ms to 7200s (2 hours). During the ON-TIME of the timer the DRV pin goes low and turns on the PMOS connecting the 5V signal to the WAKE pin initiating a wake signal. However, what about the pulse width? The answer lies in the operation of the DONE pin – when the DONE pin gets an active high pulse the DRV pin returns to a high level. If the DONE pin is not used the pulse width is the interval period of 50ms (typically). To be able to control that, two MOSFETs are added: a PMOS (Q3) and an NMOS (Q1). At the start of the drive period Q3 begins to conduct a signal into the RC timing circuit made of R1 and C1. When the voltage at C1 reaches the proper level the DRV pin returns high, shutting off Q3 but turning on Q1 to bring the DONE pins voltage back to ground so Q1 can restart the pulse again. The pulse width is some scalar multiple of the RC time constant. But what about the LDO, and why are there two MOSFETs in the circuit that are not directly used with the timer? The answer is quite simple: the sleep mode LDO must only be enabled in sleep mode. To do this, two NMOS devices (Q4 and Q5) form an inverter that allows VCC1 (either 3.3V or 5V) to shut off the LDO when VCC1 is active (for example, not in sleep or fail-safe mode) and when VCC1 shuts off, the LDO turns on powering the timer. This design allows full control of interval period, pulse width, and LDO control just from the turning on and off of VCC1. This design also has the benefit of being able to save on power unlike the 555-timer based design.