During closed-loop soft start, the FB node voltage ramps up with the reference voltage. C1 voltage is initially zero. Current must flow from FB node to C1 to charge the capacitor. The additional charge current to C1 is from V_out flowing through R1. Therefore, when C1 is charging, V_out is higher than the reference voltage determined value. At the end of the soft start ramp, there is a possibility to overshoot.

In reality, the actual V_out ramp lags VFB ramp because the system has a steady state error for a slope input. At the end of VFB ramp, the V_out lag cancels the overshoot. The VFB ramp is often flattened near the end of the ramp, which reduces the current in R3 and thus reduces the overshoot. Therefore, the actual overshoot is often invisible. The following simplified math model is for sanity check and for reference only.

Assuming the soft start ramp is strictly linear, the VFB can be expressed as a function of time.

where

• t_rise is the soft start rise time

If the ramp is infinitely long, the R3 current achieves a steady state.

The R3 current as a function of time can then be derived as:

At the end of soft start ramp, the voltage overshoot caused by C1 charging is:

Equation 21 can be used to check overshoot voltage at the end of soft start ramp. The actual overshoot amount is often approximately 50mV smaller than predicted because the soft start ramp is often flattened and gradually merges into steady state near the end. This calculation is for information only. If the overshoot is too large, the C1 value must be decreased.

To minimize C1 value needed:

1. Make R3=R4 (R3+R4 is fixed, which is discussed in Section 2.1).
2. Reduce the Margin High/Low range so that the larger R3+R4 value can be used.
3. Increase the R1 value so that larger R3+R4 value can be used.
4. Allow a higher ripple at V_out.

Alternately, increasing soft start rise time can also reduce overshoot.