SDAA302A May   2026  – August 2026 TPS53689 , TPS53689T , TPS536C9 , TPS536C9T

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Definition of Bump in Multiphase VR Systems
  6. 3System Description and Observed Error
  7. 4Simulation Analysis and Sequence of Events
  8. 5Undervoltage Fault Trigger Identification
  9. 6Measurement Validation
  10. 7Summary
  11. 8References
  12. 9Revision History

6 Measurement Validation

The analysis and simulation results were further validated through bench testing. As shown in Figure 6-1, when final INT_LOW_TC is set to 125ns, the output voltage fails to start up properly. When final INT_LOW_TC is increased to 1000ns, as shown in Figure 6-2, the output voltage is able to start up successfully. Although the internal integrator requires a calibration period during the initial start-up phase, the output voltage does not fall below the UV threshold, thereby preventing the undervoltage protection from being triggered and allowing the output voltage to ramp up normally.

Bump Reduction Enable and Final INT_LOW_TC = 125ns Figure 6-1 Bump Reduction Enable and Final INT_LOW_TC = 125ns
Bump Reduction Enable and Final INT_LOW_TC = 1000ns Figure 6-2 Bump Reduction Enable and Final INT_LOW_TC = 1000ns