The third bench test condition covers the distributed capacitance as a result of lengthy PCB traces and connectors used in between the processor to level shifter, or level shifter to flash device. The bench setup is evaluated for both 1.2V to 1.8V and 1.8V to 3.3V translation.

Figure 3-12 Heavy Distributed Capacitive Load Bench Setup, 1.2V to 1.8V

Figure 3-13 TXB0104, 1.2V to 1.8V, Output Cload = 20in. Trace + 50pF, 15MHz

Figure 3-14 Competitor, 1.2V to 1.8V, Output Cload = 20in. Trace + 50pF, 33MHz

Figure 3-15 TXB0604, 1.2V to 1.8V, Output Cload = 20in. Trace + 50pF, 33MHz

The TXB0104 and competitor device cannot accommodate long cables due to excessive parasitics; the low‑level output voltage becomes coupled to the transmission line, causing a glitch that raises VOL to nearly 800 mV. The TXB0604 observes the best signal integrity in this application.

Figure 3-16 Heavy Distributed Capacitive Load Bench Setup, 1.8V to 3.3V

Figure 3-17 TXB0104, 1.8V to 3.3V, Output Cload = 20in. Trace + 50pF, 15MHz

Figure 3-18 Competitor, 1.8V to 3.3V, Output Cload = 20in. Trace + 50pF, 15MHz

Figure 3-19 TXB0604, 1.8V to 3.3V, Output Cload = 20in. Trace + 50pF, 15MHz

The output behavior is unacceptable for the legacy and competitor waveform as the output data is drastically different from the input signal. In Figure 3-19, observe that the input signal edges become corrupted as the output side drives back into the input. The TXB0604 however, is able to observe improved signal integrity for test case in comparison to the TXB0104 and competitor device.