SDAA423 August   2026 AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2SERDES PLL SSC - Linux SDK Configuration
    1. 2.1 DTS Configuration for SSC
    2. 2.2 DTS Compiling
    3. 2.3 Device Tree Blob (DTB) Copy to SKEVM Boot-Up SD Card
  6. 3Low-Frequency Periodic Signaling (LFPS)
  7. 4CP0 - CP1 Transmission Pattern Setup
  8. 5Summary
  9. 6References

4 CP0 - CP1 Transmission Pattern Setup

The USB3.0 xHCI controller needs to be in compliance mode for all subsequent non-LFPS tests. The Port Link State Write Strobe (LWS) of the PORTSC register needs to first be set to ‘1’ to be able to write to the Port Link State (PLS) bit field of the PORTSC register. The link state can be forced to transition from Rx.Detect into compliance mode after writing to the PLS bit field and when the AM64x USB3.0 controller receiver detects a 50Ω termination. Forcing the PLS into compliance mode causes the Link Training and Status State Machine (LTSSM) to automatically jump to Polling.Compliance. The below command, which needs to be entered before connecting the USB test fixture, sets the LWS to '1' and the PLS to 10 to enable a link transtition to the Compliance state.
~# devmem2 0x0F410490 w 0x0A010340

The compliance pattern 0 (CP0), which is an 8b/10b scrambled pseudo-random data pattern (PRBS-16), is the default compliance pattern transmitted by the PHY when the USB3.0 xHCI controller transitions to compliance mode. The CP0 pattern looks like the below waveform and is used for many of the eye diagram and jitter tests.


CP0 Compliance Pattern - Oscilloscope Waveform

Figure 4-1 CP0 Compliance Pattern - Oscilloscope Waveform

The CP0 pattern is specifically used for the below tests with and without Continuous-Time Linear Equalization (CTLE).

  1. 5G Short Channel Maximum Deterministic Jitter
  2. 5G Short Channel Template Test
  3. 5G Short Channel Differential Output Voltage

The CP1 compliance pattern is a continuous 2.5GHz Nyquist clock signal for the 5Gbps data rate of the USB3.1 Gen 1 controller. This pattern is specifically important to perform the SSC and random jitter PHY compliance tests listed below.

  1. 5G TSSC - Minimum Frequency Deviation
  2. 5G TSSC - Maximum Frequency Deviation
  3. 5G SSC Modulation Rate
  4. 5G SSC Slew Rate
  5. 5G Short Channel Random Jitter (RJ)

CP0 is what the USB3.0 xHCI host controller transmits by default after entering compliance mode (Polling.Compliance). To have the TX pipeline transmit CP1 without the need of an external instrument injecting a Ping.LFPS packet for a CP0 to CP1 transition, the SuperSpeed Port Link Control register of the xHCI host controller needs to be modified by changing bits 24:21 from 4'b0000 to 4'b0001. The 2 below register writes need to be done after having booted up Linux on the AM64B SKEVM and before connecting the USB SS test fixture. The 2nd command forces CP1 to be used when entering compliance mode.

~# devmem2 0x0F410490 w 0x0A010340
~# devmem2 0x0F41812C w 0x18230C10

The CP1 2.5GHz clock signal pattern looks like the below figure.


CP1 Compliance Pattern - Oscilloscope Waveform

Figure 4-2 CP1 Compliance Pattern - Oscilloscope Waveform