SDAA468 August   2026 MSPM0G3107-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 Item definition
    2. 2.2 Assumptions
    3. 2.3 Hazard Analysis and Risk Assessment (HARA)
      1. 2.3.1 Safety Goal Definition
      2. 2.3.2 Safe State "Microcontroller Power-Cycle"
    4. 2.4 Functional Safety Concept
      1. 2.4.1 System Architecture
      2. 2.4.2 Safety Architecture
    5. 2.5 Technical Safety Concept
      1. 2.5.1 Device Description
        1. 2.5.1.1 MSPM0G3107-Q1
        2. 2.5.1.2 TPS388R0x-Q1
        3. 2.5.1.3 TPS3842C011-Q1
        4. 2.5.1.4 TPS22919-Q1
      2. 2.5.2 Implementation Details
        1. 2.5.2.1 Design Parameters
        2. 2.5.2.2 Overvoltage Protection Circuit (OVP)
        3. 2.5.2.3 Application Power Up and Power Down
        4. 2.5.2.4 TPS388R02-Q1 Software-less Operation
        5. 2.5.2.5 VCORE and VDD Monitoring
      3. 2.5.3 Monitoring Mechanisms
        1. 2.5.3.1 Monitoring VIN Supply Rail for OV Fault Including Protection
        2. 2.5.3.2 Monitoring MCU Supply Voltages for UV or OV Faults
        3. 2.5.3.3 Monitoring CPU processing Unit Program Flow
      4. 2.5.4 FMEA
        1. 2.5.4.1 Safety Mechanisms
          1. 2.5.4.1.1 SM1: MSPM0G3107-Q1 BIST and Software Test
          2. 2.5.4.1.2 SM2: TPS388R02-Q1 BIST and Internal Fault Detection
          3. 2.5.4.1.3 SM3: MSPM0G3107-Q1 VCORE Monitoring
          4. 2.5.4.1.4 SM4: MSPM0G3107-Q1 VDD Monitoring
          5. 2.5.4.1.5 SM5: Overvoltage Protection
    6. 2.6 Technical Safety Requirements
      1. 2.6.1 FMEDA for Safety Goal SG_01
        1. 2.6.1.1 Notes
      2. 2.6.2 Quantitative Results
  6. 3Summary
  7. 4References

Trademarks

Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere.

All trademarks are the property of their respective owners.