Slowing down the ACDRVx drive voltage by increasing the series resistance from ACDRVx to FET gate and/or adding a gate to source capacitor is one way to slow down a FET's turn on (i.e. soft start the FET). However, the BQ2579x family's 15ms FET detection algorithm can false trip without careful sizing of that resistor and capacitor. Another way to implement FET inrush control is to add more capacitance between the FET's gate and drain, C_DG-ADD. Figure 2-2 shows the schematic for one of the BQ25798 input MUX FET pairs and the additional gate to drain capacitance C_DG-ADD.

If C_DG-ADD is at least an order of magnitude higher than the FET's inherent C_DG, the inherent C_DG (typically in the 1000pF range) can be ignored and FET turn on time is proportional to C_GD-ADD charge time. The ACDRVx pin's output is essentially a current source with typical output current of I_ACDRV = 45uA. So, equation 1 above can be used to predict C_DG-ADD charge time and VBUS turn on time.

The additional C_DG-ADD must be sized

1. Large enough to meet the desired inrush current spec, I_IN-RUSH = (C_VBUS+C_PMID) * dV_BUS/dt. Because the ACDRVx current source charges the C_DG-ADD, the FET turn on time and therefore VBUS rise time can be estimated by the equation I_ACDRV = C_DG-ADD(MIN) * V_BUS/dt.
2. Small enough to prevent a current pulse at initial power up, i.e. C_DG-MAX = I_CDG-VACi / (d_VACi/dt) where d_VACi/dt is the VACx voltage rise time (CH1 initial rise in Figure 2),
3. Small enough that the FET turns fully on (i.e. has lowest R_DSON from ACDRVx=VBUS+5V)
   1. Before the charger's converter starts, 200ms after VBUS is higher than UVLO (3.6V typical)
   2. So that the FET does not heat up enough to exceed the safe operating area (SOA).

Note that when a fully-on wall adapter is hot-plugged, VACx sees a voltage with very high slew rate (d_VACi/dt) that causes an initial current pulse due to C_DG-ADD. In this case, C_DG-MAX computes too small to minimize the MUX FET inrush current. Adding a small series resistor (10W) reduces I_CDG-VACi. If the additional series resistance does not reduce I_CDG-VACi enough, the only choice for soft starting the MUX input FET is to use additional C_DG capacitance and higher series resistor between ACDRVx and NFET gate.

Luckily, most recent battery-powered end equipment use USB-C port for power. USB-C ports regulate the output voltage slew rate to 30mV/us. In general, C_DG-ADD works for end equipment powered by USB-C ports and other slow turn on power sources.