Digital isolators with overvoltage-tolerant inputs allow designers to simplify power‑sequencing in their applications. The isolation channel can be powered up or down independently of the surrounding logic, while the data bus remains correctly defined. This reduces the need for complex sequencing logic and enhances overall system robustness, especially in applications where the MCU must remain active while other devices are still initializing.

On a digital isolator without overvoltage-tolerant inputs, applying an input signal when the isolator is powered down can cause the current to back feed into the internal diode structures through the primary side and can cause damage to the isolator. Due to this, designers often need to be more attentive to when components power up in relation to the isolator power up time, often requiring added components for added protection to avoid stressing the isolator.

On a digital isolator with overvoltage-tolerant inputs, the isolator is designed to be less sensitive to power‑up and power‑down transients. Because the input pins can withstand voltages higher than the isolator's own supply, a logic‑level signal may be driven onto the input even when the supply of the isolator is still powered down.

This allows for the timing of the data path to be independent from the power‑sequencing of the isolation channel, allowing the MCU (or any upstream driver) to remain active throughout system start‑up and shutdown without risking latch‑up or damage to the isolator.

Figure 3-2 illustrates this behavior for an ISO6441 digital isolator. The waveforms show three simultaneous signals (Table 3-2):