SDAA607 November 2026 LMX2581
Figure 3-4 shows an example of a phase noise plot with an inappropriate loop filter. A 3rd order filter is used while a 100pF capacitor, which is far smaller than recommended, is placed near the Vtune pin C3. Therefore, the phase noise from 100kHz to 1MHz increases by approximately 10dBc, which leads to the RMS jitter (12kHz-20MHz) of 364fs.
Figure 3-4 Phase Noise Plot With C3 = 100pFHigher phase detector frequency and higher charge pump gain can reduce the jitter. This relationship is proven by adjusting the settings in TICS PRO. Loop filter components are C2 = 47nF, R2 = 357Ω, and C3 = 1.5nF (C1 is NC as C3 is close to Vtune pin). Table 3-1 shows the results of each test. Furthermore, the results indicate that the output power also influences the jitter performance, even though the output power needs to be selected based on the output swing and slew rate required by the receiver.
| Test | Doubler | Kpd/uA | Output Pwr | Jitter/fs |
|---|---|---|---|---|
| 1 | 2x | 3100 | 25 | 137.4 |
| 2 | 1x | 3100 | 25 | 188.7 |
| 3 | 2x | 2500 | 25 | 151.1 |
| 4 | 2x | 2100 | 25 | 168.6 |
| 5 | 2x | 3100 | 30 | 137.7 |
| 6 | 2x | 3100 | 20 | 139 |
Figure 3-5 TICS PRO LMX2581 ViewDifferent capacitance values for C2 and C3 have also been tried to figure out the best combinations. R2 is kept at 357Ohm for simplicity. The PLL setting is Doubler = 2x, Kpd = 3100uA, Output Pwr = 25. Along with the phase noise plot, the results prove that wider open loop bandwidth (smaller C3) helps suppress the VCO noise though the VCO phase noise can be slightly raised.
| Test | C2/nF | C3/nF | Jitter/fs |
|---|---|---|---|
| 1 | 47 | 3.3 | 159 |
| 2 | 47 | 2.2 | 147.8 |
| 3 | 47 | 1.5 | 137.4 |
| 4 | 15 | 1.5 | 143 |
| 5 | 68 | 1.5 | 138 |
Figure 3-6 Phase Noise Plot With Optimized Loop Filter