SDAA607 November   2026 LMX2581

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Design
  6. 3Loop Filter Components Selection
    1. 3.1 Design Example
    2. 3.2 Simulation in TI PLLatinum Sim
    3. 3.3 Test Verification
      1. 3.3.1 Setup
      2. 3.3.2 Test Results
  7. 4References

2 Hardware Design

Good schematic and layout are basis for better jitter performance, which happens before the loop filter component selection. In addition to the recommendations in the datasheet, other design practices include:

  1. Use high PSRR and low noise LDO to power the LMX2581 and the XO which provides the input reference clock. In this case, TPS7A84 is used. When a single regulator is used, isolating different supply pins by adding ferrite bead and capacitor on each supply pin can be helpful.
  2. Preserve at least 3rd-order loop filter like Figure 2-1. The filter can be degraded to a 2nd-order loop filter by removing C3_LF and short R3_LF.
    LMX2581 Typical Loop Filter Figure 2-1 Typical Loop Filter
  3. Place the C3_LF close to the Vtune pin on the same side of the device. The charge pump output and Vtune input are on opposite sides of the chip. In compact designs like a GPU card, the wire connection routes through internal layers then back to the surface. A close capacitor to the Vtune pin lowers the VCO noise. In 2nd-order filter design, the capacitance for C1_LF can be distributed between the normal spot and the spot of C3_LF. This arrangement can yield better performance as the footprint on the PCB for C3_LF is much closer to the VCO than the footprint for C1_LF.