SDAA607 November   2026 LMX2581

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Design
  6. 3Loop Filter Components Selection
    1. 3.1 Design Example
    2. 3.2 Simulation in TI PLLatinum Sim
    3. 3.3 Test Verification
      1. 3.3.1 Setup
      2. 3.3.2 Test Results
  7. 4References

1 Introduction

The key function block of the frequency synthesizer (or clock generator) is the phase locked loop (PLL). Figure 1-1 presents a simplified PLL structure, which is a reference-feedback-based close loop.

LMX2581 PLL Structure Figure 1-1 PLL Structure

Equation 1 calculates the target output frequency. However, optimizing the jitter requires multiple considerations.

Equation 1. f O U T = f V C O D = N R · D × f o s c

Clock jitter is an integration of phase noise in the frequency domain with a specified low and high frequency offset limit (like 12kHz-20MHz). Figure 1-2 demonstrates the dominance portion of phase noise across frequency. The PLL noise (phase detector noise, N divider noise) and VCO noise play key roles in the 12kHz-20MHz range.

LMX2581 Phase Noise Curve Figure 1-2 Phase Noise Curve

Figure 1-3 shows the simplified internal blocks of the LMX2581 and external components. Multiple Core VCO are integrated, and the loop filter needs to be implemented externally. To optimize the jitter, make an effort to tune the loop filter components and configure the dividers, charging pump gain, and other components.

LMX2581 LMX2581 Simplified Schematic Figure 1-3 LMX2581 Simplified Schematic