SFFSAD4 May 2025 TLV3511-Q1 , TLV3512-Q1
4.1.1 5-Pin Packages with OUT on Pin 1 (Northwest Pinout)
Figure 4-1 shows the pin diagram for the TLV3511-Q1. For a detailed description of the device pins, see the Pin Configuration and Functions section in the data sheet.
Figure 4-1 Pin DiagramTable 4-2 Pin FMA for Device Pins
Short-Circuited to Negative Supply (V-) Pin
| Pin Analysis for Pin Short-Circuit to Negative Supply (V-) | |||||
|---|---|---|---|---|---|
| Pin Name | Pin No. | Device Damage | Device Functionality Affected | Description of Potential Failure Effects|Comments | Failure Effect Class |
| OUT | 1 | Potentially | Yes | Thermal stress due to high power dissipation | B |
| (V-) | 2 | No | No | No change if same node as (V-) | D |
| IN+ | 3 | No | No | Output goes low, if other input is positive | C |
| IN- | 4 | No | No | Output goes high, if other input is positive | C |
| (V+) | 5 | Potentially | Yes | Main supply shorted out (no power to device) | B |
Table 4-3 Pin FMA for Device Pins
Short-Circuited to Positive Supply (V+) Pin
| Pin Analysis for Pin Short-Circuit to Positive Supply (V+) | |||||
|---|---|---|---|---|---|
| Pin Name | Pin No. | Device Damage | Device Functionality Affected | Description of Potential Failure Effects|Comments | Failure Effect Class |
| OUT | 1 | Potentially | Yes | Thermal stress due to high power dissipation | B |
| (V-) | 2 | Potentially | Yes | Main supply shorted out (no power to device) | B |
| IN+ | 3 | No | No | Output goes high, if other input is less positive | C |
| IN- | 4 | No | No | Output goes low, if other input is less positive | C |
| (V+) | 5 | No | No | No change if same node as (V+) | D |
Table 4-4 Pin FMA for Device Pins Short-Circuited to
Adjacent Pin
| Pin Analysis for Pin Short-Circuit to Adjacent Pin | |||||
|---|---|---|---|---|---|
| Pin Name | Pin No. | Device Damage | Device Functionality Affected | Description of Potential Failure Effects|Comments | Failure Effect Class |
| OUT to (V-) | 1 → 2 | Potentially | Yes | Thermal stress due to high power dissipation | B |
| (V-) to IN+ | 2 → 3 | No | No | Output goes low, if other input is positive | C |
| IN+ to IN- | 3 → 4 | No | No | Output is potentially low or high | C |
| IN- to (V+) | 4 → 5 | No | No | Output goes low, if other input is less positive | C |
| (V+) to OUT | 5 → 1 | Potentially | Yes | Thermal stress due to high power dissipation | B |
Table 4-5 Pin FMA for Device Pins Open-Circuited
| Pin Analysis for Pin Open-Circuit | |||||
|---|---|---|---|---|---|
| Pin Name | Pin No. | Device Damage | Device Functionality Affected | Description of Potential Failure Effects|Comments | Failure Effect Class |
| OUT | 1 | No | Yes | Output cannot drive application load | B |
| (V-) | 2 | Potentially | Yes | Lowest voltage pin drives GND pin internally (through a diode) | B |
| IN+ | 3 | No | No | Output is potentially low or high | C |
| IN- | 4 | No | No | Output is potentially low or high | C |
| (V+) | 5 | Potentially | Yes | Main supply open (no power to device) | B |