SFFSAD4 May 2025 TLV3511-Q1 , TLV3512-Q1
4.2.1 8-Pin Leaded Packages
Figure 4-2 shows the pin diagram for the TLV3512-Q1. For a detailed description of the device pins, see the Pin Configuration and Functions section in the data sheet.
Figure 4-2 Pin DiagramTable 4-6 Pin FMA for Device Pins Short-Circuited to
Negative Supply (V-) Pin
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| OUT1 | 1 | Thermal stress due to higher power dissipation | A |
| IN1- | 2 | OUT1 goes high if IN1+ is more positive | B |
| IN1+ | 3 | OUT1 goes low if IN1- is more positive | B |
| (V-) | 4 | Normal operation | D |
| IN2+ | 5 | OUT2 goes low if IN2- is more positive | B |
| IN2- | 6 | OUT2 goes high if IN2+ is more positive | B |
| OUT2 | 7 | Thermal stress due to higher power dissipation | A |
| (V+) | 8 | Main supply shorted out (no power to device) | B |
Table 4-7 Pin FMA for Device Pins Short-Circuited to
Positive Supply (V+) Pin
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| OUT1 | 1 | Thermal stress due to high power dissipation | A |
| IN1- | 2 | OUT1 goes low if IN1+ is less positive | B |
| IN1+ | 3 | OUT1 goes high if IN1- is less positive | B |
| (V-) | 4 | Main supply shorted out (no power to device) | B |
| IN2+ | 5 | OUT2 goes high if IN2- is less positive | B |
| IN2- | 6 | OUT2 goes low if IN2+ is less positive | B |
| OUT2 | 7 | Thermal stress due to high power dissipation | A |
| (V+) | 8 | No change (same node) | D |
Table 4-8 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| OUT1 | 1 | IN1- | OUT1 is potentially high or low | B |
| IN1- | 2 | IN1+ | OUT1 is potentially high or low | B |
| IN1+ | 3 | (V-) | OUT1 goes low, if IN1- is more positive | B |
| (V-) | 4 | IN2+ | OUT2 goes low, if IN2- is more positive | B |
| IN2+ | 5 | IN2- | OUT2 is potentially high or low | B |
| IN2- | 6 | OUT2 | OUT2 is potentially high or low | B |
| OUT2 | 7 | (V+) | Thermal stress due to higher power dissipation | A |
| (V+) | 8 | OUT1 | Thermal stress due to higher power dissipation | A |
Table 4-9 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| OUT1 | 1 | OUT1 cannot drive application load or toggle high | B |
| IN1- | 2 | OUT1 is potentially high or low | B |
| IN1+ | 3 | OUT1 is potentially low or high | B |
| (V-) | 4 | Lowest voltage pin drives (V-) pin internally (through a diode) | B |
| IN2+ | 5 | OUT2 is potentially high or low | B |
| IN2- | 6 | OUT2 is potentially high or low | B |
| OUT2 | 7 | OUT2 cannot drive application load or toggle high | B |
| (V+) | 8 | Main supply open (no power to device) | B |