SGLS162J April   2003  – June 2025 TPS793-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Shutdown
      3. 6.3.3 Foldback Current Limit
      4. 6.3.4 Thermal Protection
      5. 6.3.5 Reverse Current Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Exiting Dropout
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Capacitor Requirements
        2. 7.2.2.2 Adjustable Operation
          1. 7.2.2.2.1 Adjustable Operation (Legacy Chip)
          2. 7.2.2.2.2 Adjustable Operation (New Chip)
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 7.4.1.2 Power Dissipation and Junction Temperature
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.1 External Capacitor Requirements

A 0.1μF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS793-Q1, is required for stability. This capacitor improves transient response, noise rejection, and ripple rejection. A higher-value electrolytic input capacitor is necessary if large, fast, rise-time load transients are anticipated and the device is located several inches from the power source.

The TPS793-Q1 requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitor for the legacy chip is 2.2μF. The minimum recommended capacitance for the new chip is 0.47μF. Any 2.2μF or larger ceramic capacitor is permissible, provided the capacitance does not vary significantly over temperature.

The internal voltage reference is a key source of noise in an LDO regulator. The TPS793-Q1 (legacy chip) has a BYPASS pin that is connected to the voltage reference through a 250kΩ internal resistor. The 250kΩ internal resistor, in conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low pass filter. This filter reduces the voltage reference noise and, therefore, the noise at the regulator output. For the regulator to operate properly, make sure the current flow out of the BYPASS pin is at a minimum. Any leakage current creates an IR drop across the internal resistor, thus creating an output error. Therefore, make sure the bypass capacitor has minimal leakage current.