SGLS367F September   2006  – March 2025 SN65HVD30-EP , SN65HVD33-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Dissipation Ratings
    6. 6.6  Electrical Characteristics: Driver
    7. 6.7  Electrical Characteristics: Receiver
    8. 6.8  Switching Characteristics: Driver
    9. 6.9  Switching Characteristics: Receiver
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Power Standby Mode
      2. 8.3.2 Driver Output Current Limiting
      3. 8.3.3 Hot-Plugging
      4. 8.3.4 Receiver Failsafe
      5. 8.3.5 Safe Operation With Bus Contention
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6 Electrical Characteristics: Driver

over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
VI(K)Input clamp voltageII = –18mA–1.5V
|VOD(SS)|Steady-state differential output voltageIO = 02.3VCC + 0.1V
RL = 54Ω, See Figure 7-1 (RS-485)1.52
RL = 100Ω, See Figure 7-1 (RS-422)22.3
Vtest = –7V to 12V, See Figure 7-21.5
Δ|VOD(SS)|Change in magnitude of steady-state differential output voltage between statesRL = 54Ω, See Figure 7-1 and Figure 7-2–0.20.2V
VOD(RING)Differential output voltage overshoot and undershootRL = 54Ω, CL = 50pF, See Figure 7-5 and Figure 7-310%(2)V
VOC(PP)Peak-to-peak common-mode output voltage'HVD30, 'HVD33See Figure 7-40.5V
VOC(SS)Steady-state common-mode output voltageSee Figure 7-41.62.3V
ΔVOC(SS)Change in steady-state common-mode output voltageSee Figure 7-4–0.050.05V
IZ(Z) or
IY(Z)		High-impedance state output current'HVD30 VCC = 0V, VZ or VY = 12V,
Other input at 0V		90μA
VCC = 0V, VZ or VY = –7V,
Other input at 0V		–10
'HVD33VCC = 3V or 0V, DE = 0 V,
VZ or VY = 12V		Other input
at 0V		90
VCC = 3V or 0V, DE = 0V,
VZ or VY = –7V		–10
IZ(S) or
IY(S)		Short-circuit output currentVZ or VY = –7VOther input
at 0 V		±250mA
VZ or VY = 12V
IIInput currentD, DE0100μA
C(OD)Differential output capacitanceVOD = 0.4 sin (4E6πt) + 0.5V, DE at 0V16pF
(1) All typical values at 25°C with 3.3V supply
(2) 10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485