SLAA558A November   2012  – October 2018 MSP430F5212 , MSP430F5214 , MSP430F5217 , MSP430F5219 , MSP430F5222 , MSP430F5224 , MSP430F5229 , MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

 

  1.   Designing With MSP430F522x and MSP430F521x Devices
    1.     Trademarks
    2. 1 Split-Supply I/O Systems
    3. 2 DVIO Supplied I/Os
    4. 3 Secondary Digital Functions on DVIO Supplied I/Os
    5. 4 Split-Supply Power-Up or Power-Down Sequence
    6. 5 Reset and NMI Pin Functionality
    7. 6 XT1 and XT2 Oscillators in Bypass Mode
    8. 7 Bootloader (BSL)
      1. 7.1 BSL Entry Sequence for DVIO Supplied BSL Interface
      2. 7.2 BSL Exit Sequence for DVIO Supplied BSL Interface
    9. 8 Debugger Connections
      1. 8.1 JTAG Standard Interface
      2. 8.2 Spy-Bi-Wire Interface
      3. 8.3 Debugging Without DVIO
    10. 9 References
  2.   Revision History

7 Bootloader (BSL)

The BSL enables users to program the flash memory or RAM using a serial interface. The F522x and F521x devices come with UART as the default BSL serial interface. Access to the device memory through the BSL is protected by a user-defined password. Because the F522x and F521x devices have split I/O power domains, it is possible to interface with the BSL from either the DVCC or DVIO supply domain.

Table 1 lists the device pins used for DVCC and DVIO supplied BSL interfaces. For more details, see the BSL description in MSP430F522x, MSP430F521x Mixed-Signal Microcontrollers.

Table 1. DVCC and DVIO Supplied BSL Interfaces

BSL Function DVCC Supplied BSL Interface DVIO Supplied BSL Interface
External Reset RSTDVCC/SBWTDIO RST/NMI
Enable BSL TEST/SBWTCK BSLEN
Data Transmit P1.1 (Timer_A UART) P3.3/UCA0TXD (USCI_A0 UART)
Data Receive P1.2 (Timer_A UART) P3.4/UCA0RXD (USCI_A0 UART)
Device Power Supply DVCC, AVCC DVCC, AVCC
I/O Power Supply DVIO DVIO
Ground Supply DVSS DVSS

For single-supply systems (DVIO connected to DVCC) in which the DVCC supplied BSL interface is used, specific BSL entry and exit sequences are generated using the RSTDVCC/SBWTDIO and TEST/SBWTCK pins. These are the standard RESET and TEST based BSL entry and exit sequences that apply to all non-USB F5xx and F6xx devices, and the standard TI supplied BSL tools can be used to access the device.

For split-supply I/O systems in which the DVIO supplied BSL interface is used, specific BSL entry and exit sequences should be generated using the RST/NMI and BSLEN pins, and these sequences apply only to the DVIO supplied BSL interface.

NOTE

The default BSL loaded on these devices is the timer-based UART BSL in the DVCC domain. The USCI-based UART BSL in the DVIO domain must be loaded onto the device before being used. See the device user guide for more information. Also see the MSPBSL_CustomBSL430 Software download on the MSPBSL page for the DVIO-domain BSL image.