SLAAE56A November 2022 – March 2023 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346
MSPM0 and STM32G0 both support serial peripheral interface (SPI). Overall, MSPM0 and STM32G0 SPI support is comparable with the difference listed in #GUID-94B3612E-BC4E-4603-BADD-57C3C6A9E0BE/GUID-1F9BFADB-3531-45AC-B7EB-828FB69EEA14.
Feature | STM32G0x | MSPM0L and MSPM0G |
---|---|---|
Controller or peripheral operation | Yes | Yes |
Data bit width (controller mode) | 4 to 16 bit | 4 to 16 bit |
Data bit width (peripheral mode) | 4 to 16 bit | 7 to 16 bit |
Maximum speed | 32 MHz | MSPM0L: 16 MHz |
MSPM0G: 32 MHz | ||
Full-duplex transfers | Yes | Yes |
Half-duplex transfer (bidirectional data line) | Yes | No |
Simplex transfers (unidirectional data line) | Yes | Yes |
Multiple controller capability | Yes | No |
Hardware chip select management | Yes (1 peripheral) | Yes (4 peripherals) |
Programmable clock polarity and phase | Yes | Yes |
Programmable data order with MSB-first or LSB-first shifting | Yes | Yes |
SPI format support | Motorola, TI | Motorola, TI, MICROWIRE |
Hardware CRC | Yes | No, MSPM0 offers SPI parity mode |
TX FIFO depth | Depends on data size | 4 |
RX FIFO depth | Depends on data size | 4 |