SLAAE75A November   2022  – March 2023 MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   Abstract
  2.   Trademarks
  3. 1 MSPM0L Hardware Design Check List
  4. 2 Power Supplies in MSPM0L Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
  5. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
  6. 4 Clock System
    1. 4.1 Internal Oscillators
    2. 4.2 External Clock Output (CLK_OUT)
    3. 4.3 Frequency Clock Counter (FCC)
  7. 5 Debugger
    1. 5.1 Debug Port Pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
  8. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 OPA Design Considerations
    3. 6.3 DAC Design Considerations
    4. 6.4 COMP Design Considerations
    5. 6.5 GPAMP Design Considerations
  9. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 I2C and SPI Design Considerations
  10. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 High Speed GPIOs
    4. 8.4 Open-Drain GPIOs Enable 5-V Communication Without a Level Shifter
    5. 8.5 Communicate With 1.8-V Devices Without a Level Shifter
    6. 8.6 Unused Pins Connection
  11. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  12. 10Bootloader
    1. 10.1 Bootloader Introduction
    2. 10.2 Bootloader Hardware Design Considerations
      1. 10.2.1 Physical Communication interfaces
      2. 10.2.2 Hardware Invocation
  13. 11References
  14. 12Revision History

7.2 UART and LIN Resources and Design Considerations

The MSPM0 L series MCU includes Universal Asynchronous Receiver-Transmitter (UART). As seen in Table 7-2, UART0 supports LIN, DALI, IrDA, ISO7816 Manchester Coding function.

Table 7-2 UART Features
UART Features UART0 (Extend) UART1 (Main)
Active in Stop and Standby Mode Yes Yes
Separate transmit and receive FIFOs Yes Yes
Support hardware flow control Yes Yes
Support 9-bit configuration Yes Yes
Support LIN mode Yes -
Support DALI Yes -
Support IrDA Yes -
Support ISO7816 Smart Card Yes -
Support Manchester coding Yes -
Table 7-3 MSPM0L UART Specifications
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
fUART UART input clock frequency 32 MHz
fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 4 MHz
tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 5 5.5 32 ns
AGFSELx = 1 8 15 55 ns
AGFSELx = 2 18 38 115 ns
AGFSELx = 3 30 74 165 ns

The MSPM0L UART module can support up to 4-MHz baud date, this can support almost all UART applications.

Local Interconnect Network (LIN) is a commonly used low-speed network interface that consists of a commander node communicating with multiple remote responder nodes. Only a single wire is required for communication and is commonly included in the vehicle wiring harness.

The TLIN1021A-Q1 transmitter supports data rates up to 20 kbps. The transceiver controls the state of the LIN bus through the TXD pin and reports the state of the bus on its open-drain RXD output pin. The device has a current-limited wave-shaping driver to reduce electromagnetic emissions (EME).

The TLIN1021A-Q1 is designed to support 12-V applications with a wide input voltage operating range. The device supports low-power sleep mode, as well as wake-up from low-power mode via wake over LIN, the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present on a node through the TLIN1021A-Q1 INH output pin. #FIG_FGY_XW3_GVB shows a typical interface implemented using the TI TLIN1021A LIN transceiver.

GUID-F95B039E-FCFA-4FB1-975B-B03DA1111EE7-low.png Figure 7-1 Typical LIN TLIN1021A Transceiver

Only a single wire is required for communication and is commonly included in the vehicle wiring harness. #FIG_DFK_153_GVB#FIG_SDW_B53_GVB shows a typical interface implemented using the TI TLIN1021A LIN transceiver, for more details please refer to the TLIN1021 data sheet.

GUID-452D63EA-A263-41DC-B4BD-4D376FC759E9-low.png Figure 7-2 Typical LIN Application(Commander) with MSPM0L
GUID-F9A69F67-B989-46FA-94C9-A40E0F2F03C8-low.png Figure 7-3 Typical LIN Application(Responder) with MSPM0L