SLAAEC5A September   2024  – August 2025

 

  1.   1
  2. 1 Description
  3. 2 Required Peripherals
  4. 3 Design Steps
  5. 4 Design Considerations
  6. 5 Software Flow Chart
  7. 6 Application Code
  8. 7 Results
  9. 8 Additional Resources
  10. 9 Revision History
  11. 10E2E
  12. 11Trademarks

4 Design Considerations

  1. PWM frequency: The PWM frequency is related to the DAC resolution by:
    Equation 1. 2 N =   f C L O C K f P W M

    where

    • fCLOCK is the clock frequency of the timer
    • fPWM is the output PWM frequency
    • N is the duty-cycle resolution of the PWM DAC in bits.

    This subsystem example uses either a 32MHz clock frequency or a 16MHz clock frequency to create a 10-bit DAC. Table 4-1 details some example PWM DAC resolutions based on clock and PWM frequencies.

  2. PWM configuration: This application configures the Timer for edge-aligned PWM, and sets the capture compare updated value to take effect after the zero event.
  3. Synchronization of duty cycle update: Shadow registers are used to prevent missed counter compare value updates. This is done in MSPM0 by enabling the shadow load functionality of an appropriate timer instance. This allows the duty cycle to be updated while the timer is running, without worry of a glitch in duty cycle output.
  4. PWM Interrupt configuration: Here the timers are configured in down-count mode, so the interrupt is configured to occur a capture or compare down event. If updating the duty cycle on the very next cycle is desired, using the capture compare down or up interrupt helps make sure the captured value can be updated before the next load event or zero event. Any other system interrupt can be used as well, and needs to be synchronized by the enabling of the shadow load capability.
  5. Sample array: When outputting a signal or waveform greater than the number of samples results in a higher resolution output. The samples values need to be formatted to align with the resolution of the PWM DAC.
  6. Filter design: A basic RC filter is usually enough to filter the PWM output. The filter cutoff frequency needs to be at least an order of magnitude below the PWM frequency.

    If better filtering of the PWM edges is desired, a higher order or more complex filter can be employed.

Table 4-1 PWM DAC Resolutions
fCLOCK fPWM N
32MHz 125kHz 8
32MHz 31.3kHz 10
32MHz 7.8kHz 12
16MHz 62.5kHz 8
16MHz 15.6kHz 10
16MHz 3.9kHz 12